Don MacMillen

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Paedagogische Hochschule Heidelberg

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Université du Québec en Outaouais

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Panteion University of Social and Political Sciences

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UNIVERSITY OF THESSALY, GREECE

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Ankara University

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Tampere University

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Papers by Don MacMillen

a Nonperturbative Study of Energy Levels: I. Quantum Anharmonic Oscillators and II. Simple Quantum Models with Variable Boundary Conditions

Nimble Compiler Environment for Agile Hardware. Volume 1

SAR 18. NUMBER OF PAGES 236 Kerry L. Hill 19b. TELEPHONE NUMBER (Include Area Code) (937) 255-654... more

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A nonperturbative study of energy levels. 1: Quantum anharmonic oscillators and 2: Simple quantum models with variable boundary conditions

ABSTRACT

Behavioral synthesis methodology for HDL-based specification and validation

Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95, 1995

This paper describes a HDL synthesis based design methodology that supports user adoption of beha... more This paper describes a HDL synthesis based design methodology that supports user adoption of behavioral-level synthesis into normal design practices. The use of these techniques increases understanding of the HDL descriptions before synthesis, and makes the comparison of pre-and post-synthesis design behavior through simulation much more direct. This increases user confidence that the specification does what the user wants, i.e. that the synthesized design matches the specification in the ways that are important to the user. At the same time, the methodology gives the user a powerful set of tools to specify complex interface timing, while preserving a user's ability to delegate decision-making authority to software in those cases where the user does not wish to restrict the options available to the synthesis algorithms. This paper describes a synthesis methodology that uses high-level synthesis (HLS) of behavioral hardware-description language (HDL) descriptions. HLS has the distinguishing characteristic that operations are automatically scheduled, i.e. assigned to states, as opposed to lower-level synthesis, in which operations are assigned to states by the user [1, 2, 3]. For example, in an HDL description of a square root function, an operand x would be loaded, a series of operations would follow, and a single result r would be returned. The read x and the write r might be fixed to particular states or times by a communication protocol, but the internal operations that compute the square root would be automatically scheduled. A prospective user of HLS will then ask a number of questions. These will likely include the following: • How can I constrain I/O operations to fall into particular cycles, or range of cycles, to meet existing protocols? • How can I constrain I/O operations to have particular timing relationships? For example, how can I constrain a data ready strobe to be synchronous with data on data ports? • How can I be confident that my interface timing specification really works with the surrounding hardware? • How can I give the scheduling software optimization opportunities when my timing specification is not rigid? For example, I might not care exactly when data was transferred, as long as a corresponding strobe remains synchronized with the data. Thus the strobe and data should be locked together, but the locked strobe/ data pair of operations could move.

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Analysis Of Image Field Placement Deviations Of A 5x Microlithographic Reduction Lens

SPIE Proceedings, 1982

ABSTRACT

Modeling and analysis of differential signaling for minimizing inductive crosstalk

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)

Many p h ysical synthesis tools interdigitate signal and power lines to reduce cross-talk, and th... more Many p h ysical synthesis tools interdigitate signal and power lines to reduce cross-talk, and thus, improve signal integrity and timing predictability. S u c h approaches are extremely e ective at reducing cross-talk at circuit speeds where inductive e ects are inconsequential. In this paper, we u s e a detailed distributed RLC model to show that inductive cross-talk e ects are substantial in long busses associated with 0.18 micron technology. Simulation experiments are then used to demonstrate that cross-talk in such high speed technologies is much better controlled by re-deploying interdigitated power lines to perform di erential signaling.

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Panel I

Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05, 2005

The notion of design for manufacturability is blurring the separation between the tasks of design... more The notion of design for manufacturability is blurring the separation between the tasks of design and manufacture. In the era of nano-technologies, the description of the design rules has retreated back to an early stage form of many conditional cases and even an art. Thus, it is important to set the metrics for the manufacturability. However, who is going to be held accountable for the final outcomes? Should the designer, the EDA developer, the manufacture engineer, or a new breed of experts take the lead to tackle the problem?

ISIS: a system for performance driven resource sharing

[1992] Proceedings 29th ACM/IEEE Design Automation Conference

Programming high performance signal processing systems in high level languages

Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays, 2010

Panelists: Devedas Varma (COO) AutoESL, Vinod Kathall (CTO) Synfora, Jeff Bier (CEO) BDTI, Don Ma... more Panelists: Devedas Varma (COO) AutoESL, Vinod Kathall (CTO) Synfora, Jeff Bier (CEO) BDTI, Don MacMillen (VP Software) Stretch, and Joseph Cavallaro (Professor) Rice University Programming high performance signal processing systems is hard. Historically there has been a trade-off between ease of programming and absolute performance. It has long been understood that while for highperformance applications FPGAs are a great implementation technology, though historically they have come with a very poor programming model. For processor style architectures, such as DSPs, C-level languages are often used. Recently, there has been an emergence of C-level languages targeting FPGAs. In this panel we will discuss high level programming models and the efficiency of various technologies: DSP processors, C programming environments for FPGAs, and a completely integrated high level programming environment for a mixed technology. Both tool vendors and actual users will present the pros and cons.

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A Review of Hardware Synthesis Techniques

Hardware/Software Co-Design, 1996

This chapter gives a general overview of hardware synthesis at the behavioral level, accompanied ... more This chapter gives a general overview of hardware synthesis at the behavioral level, accompanied by a brief look at synthesis at other levels. It is intended to give the reader an idea of the capabilities and problems of behavioral synthesis as it stands, and to give the reader a set of starting points for further exploration of the literature.

Design Technology for Systems-on-Chip

SOC Design Methodologies, 2002

Advancing technology impacts design along several vectors. Interconnect delay became dominant in ... more Advancing technology impacts design along several vectors. Interconnect delay became dominant in many designs at O.18J.1I1l; to obtain timing closure, it was necessary to unify synthesis and placement. Moving forward, increasing degradation of signal integrity will be caused by capacitive cross coupling, by inductive effects and by several other physical effects. This will require the integration of fast and accurate analysis that can drive avoidance and correction of signal integrity problems primarily in routing, as well as in synthesis and placement. Advancing technology also means increasing complexity. Verification is particularly affected by technology as exemplified by the ever-increasing simulation needs. Using hundreds of millions of devices effectively will be possible only by reusing pre-designed intellectual property (lP) effectively and by addressing system-level issues in EDA. This presentation poses EDA solutions to these challenges, gives concrete examples, and argues that complete solutions, rather than point tools, will increasingly and justifiably dominate the EDA field.

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Towards system-level electromagnetic field simulation on computing clouds

2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, 2011

ABSTRACT Cloud computing is a potential paradigm-shifter for system-level electronic design autom... more ABSTRACT Cloud computing is a potential paradigm-shifter for system-level electronic design automation tools for chip-package-board design. However, exploiting the true power of on-demand scalable computing is as yet an unmet challenge. We examine electromagnetic (EM) field simulation on cloud platforms.

Scheduling Using Behavioral Templates

32nd Design Automation Conference, 1995

This paper presents the idea of "behavioral templates" in scheduling. A behavioral template locks... more This paper presents the idea of "behavioral templates" in scheduling. A behavioral template locks several operations into a relative schedule with respect to one another. This simple construct proves powerful in addressing: (1) timing constraints, (2) sequential operation modeling, (3) pre-chaining of certain operations, and (4) hierarchical scheduling. We present design examples from industry to demonstrate the importance of these issues in scheduling.

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Quantum theory of anharmonic oscillators. II. Energy levels of oscillators with x2α anharmonicity

Journal of Mathematical Physics, 1976

This is an investigation of the energy levels of anharmonic oscillators characterized by the pote... more This is an investigation of the energy levels of anharmonic oscillators characterized by the potentials (1/2) x2+λx2α with α=2,3,⋅⋅⋅ and λ≳0. Two regimes of (λ,n) space are distinguishable: In one, the energy levels differ only slightly from the harmonic ones En=n+1/2 and in the other they differ only slightly from the purely anharmonic oscillators with En?Cαλ1/(1+α) (n+1/2)2α/(1+α), C being a constant which depends on α. The magnitude of the combination η≡λ (n+1/2)α−1 determines the regime. If this combination is ≪1, one is in the harmonic regime, and if it is ≫1, one is in the anharmonic regime. As n→∞ the ’’boundary layer’’ between the two regimes narrows. The small parameter of a perturbation theory should thus be η rather than λ. Several rapidly convergent algorithms have been developed for the calculation of the energy levels of our anharmonic oscillators, and energy level tables and graphs are presented.

Variational solutions of simple quantum systems subject to variable boundary conditions. I. A model for physisorption

The Journal of Chemical Physics, 1984

A variational solution to a model problem of a hydrogen atom near a sharp planar surface of a sem... more A variational solution to a model problem of a hydrogen atom near a sharp planar surface of a semi-infinite substrate is studied. Results are presented for the ground and excited eigenstates and dipole moments of the hydrogen atom as a function of distance from the surface for two models: (a) a system in which the half-space occupied by the solid is represented by an infinite potential step; and (b) a system in which the semi-infinite substrate is perfectly imaging subject to a boundary condition that excludes the atomic electron from the substrate. Model (b) is considered as an idealized model for physisorption, where the exclusion of the electron simulates the exchange repulsion originating from the overlap of the atomic and substrate electrons. Results for the physisorption holding potential as a function of distance from the plane are presented and discussed.

Managing on-chip inductive effects

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2002

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An industrial view of electronic design automation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000

The automation of the design of electronic systems and circuits [electronic design automation (ED... more The automation of the design of electronic systems and circuits [electronic design automation (EDA)] has a history of strong innovation. The EDA business has profoundly influenced the integrated circuit (IC) business and vice-versa. This paper reviews the technologies, algorithms, and methodologies that have been used in EDA tools and the business impact of these technologies. In particular, we will focus on four areas that have been key in defining the design methodologies over time: physical design, simulation/verification, synthesis, and test. We then look briefly into the future. Design will evolve toward more software programmability or some other kind of field configurability like field programmable gate arrays (FPGAs). We discuss the kinds of tool sets needed to support design in this environment.

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Practical Integration of Process, Device, and Circuit Simulation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985

Readily available process, device, and circuit simulation programs have been integrated into an e... more Readily available process, device, and circuit simulation programs have been integrated into an effective system for enhancing semiconductor product development. In this paper, the system will be discussed with particular emphasis on the problems encountered in making simulation tools accessible to users. Each of the primary pro grams is reviewed, and the modifications and enhancements which have been made to adapt the programs to our requirements are discussed. The problem of interpolating impurity concentration profiles between process simulation grids and device simulation grids is discussed. The link between device simulation and circuit simulation is parameter ex traction. The application of optimization techniques for parameter ex traction is considered.

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Efficient subthreshold leakage current optimization - Leakage current optimization and layout migration for 90- and 65- nm ASIC libraries

IEEE Circuits and Devices Magazine, 2006

ubthreshold leakage currents consume a significant fraction of total circuit power in 90-and 65-n... more ubthreshold leakage currents consume a significant fraction of total circuit power in 90-and 65-nm technologies. Generation of library cells for low-leakage current is important for achieving low-power applicationspecific integrated circuit (ASIC) designs. Since a typical ASIC library may contain thousands of cells, efficient techniques are required. In this article, a complete automated leakage optimization flow is presented. It includes an efficient circuit optimization engine to optimize device channel length and width while keeping cell delay increase and cell area change minimal. Optimization results show about 30% leakage current reduction with only several percent active area and dynamic power increase. The optimization flow starts with SPICE net lists, including parasitic resistancecapacitance (RC) extracted from the existing library. After leakage optimization, revised cell layouts are generated and characterized based on the optimized net lists. In addition, investigations indicate that the optimization process has little impact on cell noise margins and that new cell layout variations

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a Nonperturbative Study of Energy Levels: I. Quantum Anharmonic Oscillators and II. Simple Quantum Models with Variable Boundary Conditions

Nimble Compiler Environment for Agile Hardware. Volume 1

SAR 18. NUMBER OF PAGES 236 Kerry L. Hill 19b. TELEPHONE NUMBER (Include Area Code) (937) 255-654... more

Download

A nonperturbative study of energy levels. 1: Quantum anharmonic oscillators and 2: Simple quantum models with variable boundary conditions

ABSTRACT

Behavioral synthesis methodology for HDL-based specification and validation

Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95, 1995

Download

Analysis Of Image Field Placement Deviations Of A 5x Microlithographic Reduction Lens

SPIE Proceedings, 1982

ABSTRACT

Modeling and analysis of differential signaling for minimizing inductive crosstalk

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)

Download

Panel I

Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05, 2005

ISIS: a system for performance driven resource sharing

[1992] Proceedings 29th ACM/IEEE Design Automation Conference

Programming high performance signal processing systems in high level languages

Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays, 2010

Download

A Review of Hardware Synthesis Techniques

Hardware/Software Co-Design, 1996

Design Technology for Systems-on-Chip

SOC Design Methodologies, 2002

Download

Towards system-level electromagnetic field simulation on computing clouds

2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, 2011

Scheduling Using Behavioral Templates

32nd Design Automation Conference, 1995

Download

Quantum theory of anharmonic oscillators. II. Energy levels of oscillators with x2α anharmonicity

Journal of Mathematical Physics, 1976

Variational solutions of simple quantum systems subject to variable boundary conditions. I. A model for physisorption

The Journal of Chemical Physics, 1984

Managing on-chip inductive effects

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2002

Download

An industrial view of electronic design automation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000

Download

Practical Integration of Process, Device, and Circuit Simulation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985

Download

Efficient subthreshold leakage current optimization - Leakage current optimization and layout migration for 90- and 65- nm ASIC libraries

IEEE Circuits and Devices Magazine, 2006

Download

a Nonperturbative Study of Energy Levels: I. Quantum Anharmonic Oscillators and II. Simple Quantum Models with Variable Boundary Conditions

Don MacMillen

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