ABSTRACT This chapter reviews the progress and current critical issues on the integration of germ... more ABSTRACT This chapter reviews the progress and current critical issues on the integration of germanium (Ge) surface channel MOSFET devices as well as strained Ge buried channel MOSFET structures. The device design and scalability of the strained Ge buried channel MOSFETs are discussed based on our recent results. CMOS compatible integration approaches of Ge channel devices are presented.
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 2004
The flatband/threshold voltages (Vfb/Vt) in poly-Si gated pFETs with Hf-based gate dielectrics ar... more The flatband/threshold voltages (Vfb/Vt) in poly-Si gated pFETs with Hf-based gate dielectrics are shown to be set during poly-Si deposition and are found to remain virtually unchanged during gate implantation and activation, independent of the p-type dopant. The reaction of Si with HfO2 at poly-Si deposition temperatures is identified as the root cause for the poor Vfb/Vt control. No improvement
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 2004
Dual workfunction metal gated MOSFETs with CVD TaSiN, W and Re have been fabricated on HfO2. Tinv... more Dual workfunction metal gated MOSFETs with CVD TaSiN, W and Re have been fabricated on HfO2. Tinv as low as 1.46 nm with appropriate Vts and sub-threshold slopes 90 mV/decade or better have been achieved. For the first time we report low damage CVD processes for achieving dual workfunction metal gates in contrast to most reports in literature. Excellent hole
Digest of Technical Papers - Symposium on VLSI Technology, 2007
... High-Performance High-κ/Metal Gates for 45nm CMOS and Beyond with Gate-First Processing M. Ch... more ... High-Performance High-κ/Metal Gates for 45nm CMOS and Beyond with Gate-First Processing M. Chudzik, B. Doris2, R. Mo, J. Sleight2, E ... References [1] J. Sleight et al., International Electron Devices Meeting (IEDM), San Fran., CA, 2006 [2] E. Cartier et al., 2005 Symposium on ...
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 2006
A scalable poly-Si/AlN/HfSiO gate stack, implementing a new aluminum nitride (AlN) cap layer, com... more A scalable poly-Si/AlN/HfSiO gate stack, implementing a new aluminum nitride (AlN) cap layer, combined with oxygen diffusion barrier, halo and counter doping engineering, high temperature spike anneal for gate and junction activation, and optional inverted gate implant, has been successfully developed to fully offset the large threshold voltage (Vt) shifts in poly-Si/HfSiO devices and achieve good thickness scalability and gate
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004., 2004
... V. Ku, R. Amos, A. Steegen, C. Cabral, Jr., V. Narayanan, P. Jamison, P. Nguyen, Y. Li, M. Gr... more ... V. Ku, R. Amos, A. Steegen, C. Cabral, Jr., V. Narayanan, P. Jamison, P. Nguyen, Y. Li, M. Gribelyuk, Y. Wang, 1. Cai, A. Callegari, F. McFeely, F. Jamin, K. Wong, E. Wu, A. Chou, D. Boyd, H. Ng, M. Ieong, C. Wann, R. Jammy, and W. Haensch, “Low Tinv(<l.Snm) metal-gated ...
We report on growth behavior, structure, thermal stability and electrical properties of ultrathin... more We report on growth behavior, structure, thermal stability and electrical properties of ultrathin (,10 nm) hafnium oxide films deposited by atomic layer deposition using sequential exposures of HfCl and H O at 300 8C on a bare silicon surface 4 2 or a thin thermally grown SiO -based interlayer. Compared to good quality continuous films deposited on SiO surfaces, 2 2
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 2005
Abstract A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1... more Abstract A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is ...
ABSTRACT This chapter reviews the progress and current critical issues on the integration of germ... more ABSTRACT This chapter reviews the progress and current critical issues on the integration of germanium (Ge) surface channel MOSFET devices as well as strained Ge buried channel MOSFET structures. The device design and scalability of the strained Ge buried channel MOSFETs are discussed based on our recent results. CMOS compatible integration approaches of Ge channel devices are presented.
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 2004
The flatband/threshold voltages (Vfb/Vt) in poly-Si gated pFETs with Hf-based gate dielectrics ar... more The flatband/threshold voltages (Vfb/Vt) in poly-Si gated pFETs with Hf-based gate dielectrics are shown to be set during poly-Si deposition and are found to remain virtually unchanged during gate implantation and activation, independent of the p-type dopant. The reaction of Si with HfO2 at poly-Si deposition temperatures is identified as the root cause for the poor Vfb/Vt control. No improvement
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 2004
Dual workfunction metal gated MOSFETs with CVD TaSiN, W and Re have been fabricated on HfO2. Tinv... more Dual workfunction metal gated MOSFETs with CVD TaSiN, W and Re have been fabricated on HfO2. Tinv as low as 1.46 nm with appropriate Vts and sub-threshold slopes 90 mV/decade or better have been achieved. For the first time we report low damage CVD processes for achieving dual workfunction metal gates in contrast to most reports in literature. Excellent hole
Digest of Technical Papers - Symposium on VLSI Technology, 2007
... High-Performance High-κ/Metal Gates for 45nm CMOS and Beyond with Gate-First Processing M. Ch... more ... High-Performance High-κ/Metal Gates for 45nm CMOS and Beyond with Gate-First Processing M. Chudzik, B. Doris2, R. Mo, J. Sleight2, E ... References [1] J. Sleight et al., International Electron Devices Meeting (IEDM), San Fran., CA, 2006 [2] E. Cartier et al., 2005 Symposium on ...
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 2006
A scalable poly-Si/AlN/HfSiO gate stack, implementing a new aluminum nitride (AlN) cap layer, com... more A scalable poly-Si/AlN/HfSiO gate stack, implementing a new aluminum nitride (AlN) cap layer, combined with oxygen diffusion barrier, halo and counter doping engineering, high temperature spike anneal for gate and junction activation, and optional inverted gate implant, has been successfully developed to fully offset the large threshold voltage (Vt) shifts in poly-Si/HfSiO devices and achieve good thickness scalability and gate
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004., 2004
... V. Ku, R. Amos, A. Steegen, C. Cabral, Jr., V. Narayanan, P. Jamison, P. Nguyen, Y. Li, M. Gr... more ... V. Ku, R. Amos, A. Steegen, C. Cabral, Jr., V. Narayanan, P. Jamison, P. Nguyen, Y. Li, M. Gribelyuk, Y. Wang, 1. Cai, A. Callegari, F. McFeely, F. Jamin, K. Wong, E. Wu, A. Chou, D. Boyd, H. Ng, M. Ieong, C. Wann, R. Jammy, and W. Haensch, “Low Tinv(<l.Snm) metal-gated ...
We report on growth behavior, structure, thermal stability and electrical properties of ultrathin... more We report on growth behavior, structure, thermal stability and electrical properties of ultrathin (,10 nm) hafnium oxide films deposited by atomic layer deposition using sequential exposures of HfCl and H O at 300 8C on a bare silicon surface 4 2 or a thin thermally grown SiO -based interlayer. Compared to good quality continuous films deposited on SiO surfaces, 2 2
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 2005
Abstract A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1... more Abstract A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is ...
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Papers by M. Gribelyuk