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Manuel Anido

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Vrije Universiteit Brussel

University of Essex

Instituto Superior Técnico

Hamid R. Rabiee

Sharif University of Technology

Mohamed Laaraiedh

SupCom

Saulo Xavier de Souza

Centro Universitário do Distrito Federal – UDF Biblioteca Governador Eurico

Anatoliy Lapchuk

Institute of bioorganic chemistry and Petrochemistry NAS Ukraine

Wiktoria Wilkowska

RWTH Aachen University

American International University-Bangladesh

Thomas SchwarzSJ

Marquette University

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Papers by Manuel Anido

Projeto rede local Citibank: relatório técnico número 2

Indisponível

A Distributed Object-Oriented Design Rule Checker .PDF

VLSI algorithms are complex, dynamic, specialized, demanding CPU and memory. To support such dyna... more VLSI algorithms are complex, dynamic, specialized, demanding CPU and memory. To support such dynamic computing demands, it is necessary to employ a scalable system, which can be easily adapted and extended to run newer VLSI algorithms. This paper describes the design of a distributed object-oriented Design Rule Checker (DRC), focusing on its implementation methodology. It also proposes the use of XML to describe technology design rues. These rules were executed on a distributed OO structure. The paper also shows that by using programmable scripts that carry out a modular encapsulated structure, a robust and adaptable system can be obtained.

A survey and taxonomy of layout compaction algorithms

This paper presents a survey and a taxonomy of layout compaction algorithms, which are an essenti... more This paper presents a survey and a taxonomy of layout compaction algorithms, which are an essential part of modern symbolic layout tools employed in VLSI circuit design. Layout compaction techniques are also used in the low-end stages of silicon compilation tools and module generators. The paper addresses the main algorithms used in compaction, focusing on their implementation characteristics, performance, advantages and drawbacks. Compaction is a highly important operation to optimize the use of silicon area, achieve higher speed through wire length minimization, support technology retargeting and also allow the use of legacy layouts. Optimized cells that were developed for a fabrication process with a set of design rules have to be retargeted for a new and more compact process with a different set of design rules

A distributed system for microelectronic algorithms

Microelectronics tools tend to consume large amounts of memory and processor time. When circuit s... more Microelectronics tools tend to consume large amounts of memory and processor time. When circuit size outgrows the resources available on a station, its time for a scalable tool architecture. Applied to design rule checking of jlattened masks, this distributed; object-oriented architecture summons together the power of small, cheap desktop computers. The distributed system enables processing of larger circuits, assigning distinct parts of the problem to each machine. Larger circuits can be tested and testing time reduced as more computers are aggregated to the process

O projeto de um RISC para geração de imagens por computador

This paper describes the design and analysis of a RISC processor, designed to operate as a geomet... more This paper describes the design and analysis of a RISC processor, designed to operate as a geometry engine, for computer image generation. It presents a novel technique with DMA channels direct to the register file, a high-performance multiplier and a high-performance divider.Este relatório descreve a análise e o projeto de um processador RISC, projetado para operar como um processador geométrico, para geração de imagens por computador. Este relatório apresenta uma nova técnica com canais DMA diretos para o conjunto de registros, juntamente com um multiplicador e um circuito de divisão de alto desempenho

Um levantamento de alguns métodos e implementações de operações de multiplicação e divisão e sua aplicabilidade em microprocessadores

Apresenta um levantamento de alguns métodos e implementações de multiplicação e divisão aplicávei... more Apresenta um levantamento de alguns métodos e implementações de multiplicação e divisão aplicáveis na unidade aritmética inteira ou ponto flutuante de microprocessadores. O artigo também apresenta uma análise qualitativa e discute as principais vantagens e desvantagens de cada um dos métodos em relação aos demais

A graduate program for the educational of computer network managers

This paper describes a graduate program in Computer Network Operations, Internet Technology and O... more This paper describes a graduate program in Computer Network Operations, Internet Technology and Operating Systems' Support, organized by the Federal University of Rio de Janeiro and which has had a considerable success. One of the main contributions o this paper is the discussion of an appropriate curriculum for computer network managers. The paper discusses the main objectives and issues of the program, which are a practical application-oriented curriculum and the need to provide a strong foundation on several inter-related subject areas, other than computer network technology

Aplicação de patterns no desenvolvimento de um sistema CAD para microeletrônica

Relatório Técnico NCE, Dec 31, 1999

Palavras chaves: Programação orientada a objetos, Padrões de Projeto, circuitos integrados Resumo... more Palavras chaves: Programação orientada a objetos, Padrões de Projeto, circuitos integrados Resumo "Este artigo apresenta a aplicação de técnica de orientação a objetos para resolver problemas de integração em ferramentas de CAD para microeletrônica. A abordagem enfatiza o uso de patterns e componentização para obter homogeneidade e o reuso de software. Os componentes são responsáveis por realizar tarefas básicas como a interpretação de linguagens e edição gráfica. A divisão de arquitetura em camadas garante a modularidade e provê o acoplamento de ferramentas funcionais. A arquitetura também suporta a distribuição de objetos, aumentando o potencial de processamento em redes de computadores.

Developing a distributed architecture for design rule checking

Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)

implementation of a distributed DRC a1gorithrn, which allows the exemplification of the distribut... more implementation of a distributed DRC a1gorithrn, which allows the exemplification of the distributed architecture. This paper describes the design and implementation of a distributed object-oriented Design Rule Checker (DRC). 2.Specifying design rules The majn focus is on the methodology employed to implement this distributed application. Code reusability is 2.1.Design rule checking achieved using an 00 approach, making objects available for other tools, such as circuit extractor. The paper also Design rules usually specify minimum track width, track addresses the application of design pattems, which produce separation, and the extension of one polygon to another, loosely coupled elements, facilitating the jntegration of targeting the formation of an active element. Design rule system modules. verification is based on boolean operations (AND, OR, XOR) performed on layers containing a set of geometric forrns which usually are rectangles. This is illustrated by

Data encryption standard simulation and a bit-slice architecture design

This paper presents a high levellanguage implementation of the Data Encryption Standard (DES) and... more This paper presents a high levellanguage implementation of the Data Encryption Standard (DES) and discusses a design that employs a bit-sliced architecture. The HLL implementation was performed on Borland 's@ Delphi4TM language and proved to be highly valuable for obtaining the intermediate results that were required for debugging. The key objectives of this work were to make DES available for system applications written in the Delphi4TM language and also to discuss the design of a bit-sliced DES architecture suitable for applications requiring low silicon area.

A CAD system for teaching the design of VLSI circuits (status and evolution)

This paper presents the main characteristics of TEDMOS - a CAD (Computer Aided Design) system for... more This paper presents the main characteristics of TEDMOS - a CAD (Computer Aided Design) system for teaching the design of VLSI (Very Large Scale Integrated ) circuits. The paper starts by discussing the main assets of TEDMOS, when compared with commercial CAD systems, and presents the high-level characteristics of its main constituent programs. At the end, the paper discusses the evolution of the TEDMOS system.

The architecture of a novel tool for network management using GSM/GPRS mobile devices

2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672), 2004

Computer network management is a highly demanding task because network managers have to deal with... more Computer network management is a highly demanding task because network managers have to deal with urgent requests to solve network problems Unfortunately, a network manager may be situated in a location where there is no internet-connected computer to perform remote network management tasks. To solve this problem, this paper describes the architecture of a novel tool for network management using GSM/GPRS mobile devices. The paper starts by presenting some general concepts about network management and GPRS technology. Then it focuses on the description of architecture for the development of applications for network management. The paper also describes implementation details of a network management tool, particularly the interface for mobile devices. At the end, it shows results by depicting the screen of several mobile devices, which provide network management information.

A high level language implementation of the data encryption standard and a bit-slice architecture

Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144), 2000

This paper presents a High Level Language (HLL) implementation of the Data Encryption Standard (D... more This paper presents a High Level Language (HLL) implementation of the Data Encryption Standard (DES) and discusses an implementation that employs a bit-sliced architecture. The HLL implementation was performed on Borland's Delphi4™ language and proved to be highly valuable for obtaining the intermediate results that were required for debugging. The key objectives of this work were to make DES available for system applications written in fifth generation languages and also to discuss the design of a bitsliced DES architecture suitable for applications requiring low silicon area.

A novel tool for network management using a WAP interface

18th International Conference on Advanced Information Networking and Applications, 2004. AINA 2004.

Computer network managers are often requested to solve urgent network problems. Many times, they ... more Computer network managers are often requested to solve urgent network problems. Many times, they cannot access a computer to perform remote network management tasks. Aiming at solving this problem, this paper presents a novel tool for network management that uses a WAP interface, and focuses on the description of the architecture and the associated application modules. This paper also describes

Efficient layout editing by combining disk storage layout partitioning and cell hierarchies

Proceedings of the 39th Midwest Symposium on Circuits and Systems

... Translation: x'=x +Tx y'= y+Ty 1 Tx Ty 1 [XI y' 1]= [x y 1 ] O 1 L Rotation: -... more ... Translation: x'=x +Tx y'= y+Ty 1 Tx Ty 1 [XI y' 1]= [x y 1 ] O 1 L Rotation: -1 s' = s cos a + y sin a y' = -x cos a + y cos U, where a is multiple of 90 degrees rcos a -sina 01 sina cos a [XI y' 11 = Lx y 1 ] Scaling: x'=x* sx y'=y* sy r 1 sx 0 [x' y' l]=Cx y 11 VI. ...

Improving the division instruction of application-specific RISCs

Microprocessing and Microprogramming, 1991

Abstract This paper presents the development and application of a signed radix-4 division algorit... more Abstract This paper presents the development and application of a signed radix-4 division algorithm to a RISC architecture, where the internal ALU Manchester Carry adder is used to maintain the partial remainder in irredundant form. There are division algorithms which are faster than the one described in this paper, however, they usually make use of a redundant representation of the partial remainder and require carry-save adders which are not normally used in the integer execution unit of RISCs. The method presented in this contribution employs 3x divisor multiples and uses a reduced next divisor multiple estimate table which is implemented by a small and fast logic. Alternative radix-4 schemes with quotient digits {-2,-1,0,1,2} require large and slow PLAs for quotient digit generation. Additionally, there is no need for positive and negative quotient registers because quotient bits are generated on-the-fly by a small-sized logic, concurrently with partial remainder formation. This method also deals directly with signed two's complement numbers, eliminating the need for additional instructions for sign conversion. The application of this radix-4 division algorithm provides a two-bits-at-a-time division instruction, instead of the traditional single bit approach used in some RISCs. The speedup achieved can be very important in many numeric intensive applications, in which the use of floating-point units is not essential.

Low energy data management for different on-chip memory levels in multi-context reconfigurable architectures

This paper presents a new technique to improve the efficiency of data scheduling for multi-contex... more This paper presents a new technique to improve the efficiency of data scheduling for multi-context reconfigurable architectures targeting multimedia and DSP applications. The main goal is to improve application energy consumption. Two levels of on-chip data storage are assumed in the reconfigurable architecture. The Data Scheduler attempts to optimally exploit this storage, by deciding in which on-chip memory the data have to be stored in order to reduce energy consumption. We also show that a suitable data scheduling could decrease the energy required to implement the dynamic reconfiguration of the system.

Interactive ray tracing using a SIMD reconfigurable architecture

14th Symposium on Computer Architecture and High Performance Computing, 2002. Proceedings.

This paper presents an architecture for running interactive ray tracing applications on portable ... more This paper presents an architecture for running interactive ray tracing applications on portable devices such as cell phones, PDAs, and head mounted displays and discusses the main issues related to the mapping of this graphics algorithm using fixed-point arithmetic. The paper shows that a floatingpoint arithmetic unit, with its associated power and area consumption, can be avoided by using appropriate fixed-point arithmetic and block floating-point operations. It is also shown that a computation intensive graphics method like ray tracing can be used to generate simple images at interactive rates on portable devices. This can be achieved by employing a reconfigurable SIMD architecture on a chip, which trades parallelism for frequency of operation, thus providing significant benefits in power saving, which is essential in portable devices. Dr. M. Anido acknowledges the financial support by CNPq. This work was supported by DARPA (DoD) under contract F-33615-97-C-1126 and the National Science Foundation under grant CCR-0083080.

$Fixed point arithmetic is a type of arithmetic that uses the integer unit of the processor, where operands may have an integer part and a fractional part. When two operands are added or subtracted, a carry (borrow) bit propagates normally between the fractional part and the integer part as if the two operands were just integers[23]. Fixed point arithmetic with scaling, together with block floating point arithmetic [24] can provide similar image quality to floating point arithmetic, at an equivalent speed for basic functions such as addition, subtraction and multiplication. Figure 3 illustrates a 16-bit fixed point multiplication with scaling that is implemented in one clock cycle in each of the 64 MorphoSys SIMD processing elements. Floating point arithmetic may be necessary for graphics applications that employ a large database where the world coordinates may require a large dynamic data range. However, this is not the case for the targeted applications envisaged for the architecture described in this paper.$

Interactive Ray Tracing on Reconfigurable SIMD Morphosys

Embedded Software for SoC

MorphoSys is a reconfigurable SIMD architecture. In this paper, a BSP-based ray tracing is gracef... more MorphoSys is a reconfigurable SIMD architecture. In this paper, a BSP-based ray tracing is gracefully mapped onto MorphoSys. The mapping highly exploits ray-tracing parallelism. A straightforward mechanism is used to handle irregularity among parallel rays in BSP. To support this mechanism, a special data structure is established, in which no intermediate data has to be saved. Moreover, optimizations such as object reordering and merging are facilitated. Data starvation is avoided by overlapping data transfer with intensive computation so that applications with different complexity can be managed efficiently. Since MorphoSys is small in size and power efficient, we demonstrate that MorphoSys is an economic platform for 3D animation applications on portable devices.

Técnicas de processamento paralelo para sistemas gráficos de alto desempenho

Este artigo descreve as principais tecnicas de processamento paralelo empregadas na geracâo de im... more Este artigo descreve as principais tecnicas de processamento paralelo empregadas na geracâo de imagens por computador e apresenta as arquiteturas de alguns sistemas de visualizacâo de alto desempenho. Inicialmente este artigo analisa os problemas envolvidos na geracâo de imagens, de forma qualitativa e quantitativa. Em seguida e apresentada uma taxonomia de sistemas de geracâo de imagens, discutindo as principais vantagens e restricoes de cada um.

Projeto rede local Citibank: relatório técnico número 2

Indisponível

A Distributed Object-Oriented Design Rule Checker .PDF

VLSI algorithms are complex, dynamic, specialized, demanding CPU and memory. To support such dyna... more VLSI algorithms are complex, dynamic, specialized, demanding CPU and memory. To support such dynamic computing demands, it is necessary to employ a scalable system, which can be easily adapted and extended to run newer VLSI algorithms. This paper describes the design of a distributed object-oriented Design Rule Checker (DRC), focusing on its implementation methodology. It also proposes the use of XML to describe technology design rues. These rules were executed on a distributed OO structure. The paper also shows that by using programmable scripts that carry out a modular encapsulated structure, a robust and adaptable system can be obtained.

A survey and taxonomy of layout compaction algorithms

This paper presents a survey and a taxonomy of layout compaction algorithms, which are an essenti... more This paper presents a survey and a taxonomy of layout compaction algorithms, which are an essential part of modern symbolic layout tools employed in VLSI circuit design. Layout compaction techniques are also used in the low-end stages of silicon compilation tools and module generators. The paper addresses the main algorithms used in compaction, focusing on their implementation characteristics, performance, advantages and drawbacks. Compaction is a highly important operation to optimize the use of silicon area, achieve higher speed through wire length minimization, support technology retargeting and also allow the use of legacy layouts. Optimized cells that were developed for a fabrication process with a set of design rules have to be retargeted for a new and more compact process with a different set of design rules

A distributed system for microelectronic algorithms

Microelectronics tools tend to consume large amounts of memory and processor time. When circuit s... more Microelectronics tools tend to consume large amounts of memory and processor time. When circuit size outgrows the resources available on a station, its time for a scalable tool architecture. Applied to design rule checking of jlattened masks, this distributed; object-oriented architecture summons together the power of small, cheap desktop computers. The distributed system enables processing of larger circuits, assigning distinct parts of the problem to each machine. Larger circuits can be tested and testing time reduced as more computers are aggregated to the process

O projeto de um RISC para geração de imagens por computador

This paper describes the design and analysis of a RISC processor, designed to operate as a geomet... more This paper describes the design and analysis of a RISC processor, designed to operate as a geometry engine, for computer image generation. It presents a novel technique with DMA channels direct to the register file, a high-performance multiplier and a high-performance divider.Este relatório descreve a análise e o projeto de um processador RISC, projetado para operar como um processador geométrico, para geração de imagens por computador. Este relatório apresenta uma nova técnica com canais DMA diretos para o conjunto de registros, juntamente com um multiplicador e um circuito de divisão de alto desempenho

Um levantamento de alguns métodos e implementações de operações de multiplicação e divisão e sua aplicabilidade em microprocessadores

Apresenta um levantamento de alguns métodos e implementações de multiplicação e divisão aplicávei... more Apresenta um levantamento de alguns métodos e implementações de multiplicação e divisão aplicáveis na unidade aritmética inteira ou ponto flutuante de microprocessadores. O artigo também apresenta uma análise qualitativa e discute as principais vantagens e desvantagens de cada um dos métodos em relação aos demais

A graduate program for the educational of computer network managers

This paper describes a graduate program in Computer Network Operations, Internet Technology and O... more This paper describes a graduate program in Computer Network Operations, Internet Technology and Operating Systems' Support, organized by the Federal University of Rio de Janeiro and which has had a considerable success. One of the main contributions o this paper is the discussion of an appropriate curriculum for computer network managers. The paper discusses the main objectives and issues of the program, which are a practical application-oriented curriculum and the need to provide a strong foundation on several inter-related subject areas, other than computer network technology

Aplicação de patterns no desenvolvimento de um sistema CAD para microeletrônica

Relatório Técnico NCE, Dec 31, 1999

Palavras chaves: Programação orientada a objetos, Padrões de Projeto, circuitos integrados Resumo... more Palavras chaves: Programação orientada a objetos, Padrões de Projeto, circuitos integrados Resumo "Este artigo apresenta a aplicação de técnica de orientação a objetos para resolver problemas de integração em ferramentas de CAD para microeletrônica. A abordagem enfatiza o uso de patterns e componentização para obter homogeneidade e o reuso de software. Os componentes são responsáveis por realizar tarefas básicas como a interpretação de linguagens e edição gráfica. A divisão de arquitetura em camadas garante a modularidade e provê o acoplamento de ferramentas funcionais. A arquitetura também suporta a distribuição de objetos, aumentando o potencial de processamento em redes de computadores.

Developing a distributed architecture for design rule checking

Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)

implementation of a distributed DRC a1gorithrn, which allows the exemplification of the distribut... more implementation of a distributed DRC a1gorithrn, which allows the exemplification of the distributed architecture. This paper describes the design and implementation of a distributed object-oriented Design Rule Checker (DRC). 2.Specifying design rules The majn focus is on the methodology employed to implement this distributed application. Code reusability is 2.1.Design rule checking achieved using an 00 approach, making objects available for other tools, such as circuit extractor. The paper also Design rules usually specify minimum track width, track addresses the application of design pattems, which produce separation, and the extension of one polygon to another, loosely coupled elements, facilitating the jntegration of targeting the formation of an active element. Design rule system modules. verification is based on boolean operations (AND, OR, XOR) performed on layers containing a set of geometric forrns which usually are rectangles. This is illustrated by

Data encryption standard simulation and a bit-slice architecture design

This paper presents a high levellanguage implementation of the Data Encryption Standard (DES) and... more This paper presents a high levellanguage implementation of the Data Encryption Standard (DES) and discusses a design that employs a bit-sliced architecture. The HLL implementation was performed on Borland 's@ Delphi4TM language and proved to be highly valuable for obtaining the intermediate results that were required for debugging. The key objectives of this work were to make DES available for system applications written in the Delphi4TM language and also to discuss the design of a bit-sliced DES architecture suitable for applications requiring low silicon area.

A CAD system for teaching the design of VLSI circuits (status and evolution)

This paper presents the main characteristics of TEDMOS - a CAD (Computer Aided Design) system for... more This paper presents the main characteristics of TEDMOS - a CAD (Computer Aided Design) system for teaching the design of VLSI (Very Large Scale Integrated ) circuits. The paper starts by discussing the main assets of TEDMOS, when compared with commercial CAD systems, and presents the high-level characteristics of its main constituent programs. At the end, the paper discusses the evolution of the TEDMOS system.

The architecture of a novel tool for network management using GSM/GPRS mobile devices

2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672), 2004

Computer network management is a highly demanding task because network managers have to deal with... more Computer network management is a highly demanding task because network managers have to deal with urgent requests to solve network problems Unfortunately, a network manager may be situated in a location where there is no internet-connected computer to perform remote network management tasks. To solve this problem, this paper describes the architecture of a novel tool for network management using GSM/GPRS mobile devices. The paper starts by presenting some general concepts about network management and GPRS technology. Then it focuses on the description of architecture for the development of applications for network management. The paper also describes implementation details of a network management tool, particularly the interface for mobile devices. At the end, it shows results by depicting the screen of several mobile devices, which provide network management information.

A high level language implementation of the data encryption standard and a bit-slice architecture

Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144), 2000

This paper presents a High Level Language (HLL) implementation of the Data Encryption Standard (D... more This paper presents a High Level Language (HLL) implementation of the Data Encryption Standard (DES) and discusses an implementation that employs a bit-sliced architecture. The HLL implementation was performed on Borland's Delphi4™ language and proved to be highly valuable for obtaining the intermediate results that were required for debugging. The key objectives of this work were to make DES available for system applications written in fifth generation languages and also to discuss the design of a bitsliced DES architecture suitable for applications requiring low silicon area.

A novel tool for network management using a WAP interface

18th International Conference on Advanced Information Networking and Applications, 2004. AINA 2004.

Computer network managers are often requested to solve urgent network problems. Many times, they ... more Computer network managers are often requested to solve urgent network problems. Many times, they cannot access a computer to perform remote network management tasks. Aiming at solving this problem, this paper presents a novel tool for network management that uses a WAP interface, and focuses on the description of the architecture and the associated application modules. This paper also describes

Efficient layout editing by combining disk storage layout partitioning and cell hierarchies

Proceedings of the 39th Midwest Symposium on Circuits and Systems

... Translation: x'=x +Tx y'= y+Ty 1 Tx Ty 1 [XI y' 1]= [x y 1 ] O 1 L Rotation: -... more ... Translation: x'=x +Tx y'= y+Ty 1 Tx Ty 1 [XI y' 1]= [x y 1 ] O 1 L Rotation: -1 s' = s cos a + y sin a y' = -x cos a + y cos U, where a is multiple of 90 degrees rcos a -sina 01 sina cos a [XI y' 11 = Lx y 1 ] Scaling: x'=x* sx y'=y* sy r 1 sx 0 [x' y' l]=Cx y 11 VI. ...

Improving the division instruction of application-specific RISCs

Microprocessing and Microprogramming, 1991

Abstract This paper presents the development and application of a signed radix-4 division algorit... more Abstract This paper presents the development and application of a signed radix-4 division algorithm to a RISC architecture, where the internal ALU Manchester Carry adder is used to maintain the partial remainder in irredundant form. There are division algorithms which are faster than the one described in this paper, however, they usually make use of a redundant representation of the partial remainder and require carry-save adders which are not normally used in the integer execution unit of RISCs. The method presented in this contribution employs 3x divisor multiples and uses a reduced next divisor multiple estimate table which is implemented by a small and fast logic. Alternative radix-4 schemes with quotient digits {-2,-1,0,1,2} require large and slow PLAs for quotient digit generation. Additionally, there is no need for positive and negative quotient registers because quotient bits are generated on-the-fly by a small-sized logic, concurrently with partial remainder formation. This method also deals directly with signed two's complement numbers, eliminating the need for additional instructions for sign conversion. The application of this radix-4 division algorithm provides a two-bits-at-a-time division instruction, instead of the traditional single bit approach used in some RISCs. The speedup achieved can be very important in many numeric intensive applications, in which the use of floating-point units is not essential.

Low energy data management for different on-chip memory levels in multi-context reconfigurable architectures

This paper presents a new technique to improve the efficiency of data scheduling for multi-contex... more This paper presents a new technique to improve the efficiency of data scheduling for multi-context reconfigurable architectures targeting multimedia and DSP applications. The main goal is to improve application energy consumption. Two levels of on-chip data storage are assumed in the reconfigurable architecture. The Data Scheduler attempts to optimally exploit this storage, by deciding in which on-chip memory the data have to be stored in order to reduce energy consumption. We also show that a suitable data scheduling could decrease the energy required to implement the dynamic reconfiguration of the system.

Interactive ray tracing using a SIMD reconfigurable architecture

14th Symposium on Computer Architecture and High Performance Computing, 2002. Proceedings.

This paper presents an architecture for running interactive ray tracing applications on portable ... more This paper presents an architecture for running interactive ray tracing applications on portable devices such as cell phones, PDAs, and head mounted displays and discusses the main issues related to the mapping of this graphics algorithm using fixed-point arithmetic. The paper shows that a floatingpoint arithmetic unit, with its associated power and area consumption, can be avoided by using appropriate fixed-point arithmetic and block floating-point operations. It is also shown that a computation intensive graphics method like ray tracing can be used to generate simple images at interactive rates on portable devices. This can be achieved by employing a reconfigurable SIMD architecture on a chip, which trades parallelism for frequency of operation, thus providing significant benefits in power saving, which is essential in portable devices. Dr. M. Anido acknowledges the financial support by CNPq. This work was supported by DARPA (DoD) under contract F-33615-97-C-1126 and the National Science Foundation under grant CCR-0083080.

$Fixed point arithmetic is a type of arithmetic that uses the integer unit of the processor, where operands may have an integer part and a fractional part. When two operands are added or subtracted, a carry (borrow) bit propagates normally between the fractional part and the integer part as if the two operands were just integers[23]. Fixed point arithmetic with scaling, together with block floating point arithmetic [24] can provide similar image quality to floating point arithmetic, at an equivalent speed for basic functions such as addition, subtraction and multiplication. Figure 3 illustrates a 16-bit fixed point multiplication with scaling that is implemented in one clock cycle in each of the 64 MorphoSys SIMD processing elements. Floating point arithmetic may be necessary for graphics applications that employ a large database where the world coordinates may require a large dynamic data range. However, this is not the case for the targeted applications envisaged for the architecture described in this paper.$

Interactive Ray Tracing on Reconfigurable SIMD Morphosys

Embedded Software for SoC

MorphoSys is a reconfigurable SIMD architecture. In this paper, a BSP-based ray tracing is gracef... more MorphoSys is a reconfigurable SIMD architecture. In this paper, a BSP-based ray tracing is gracefully mapped onto MorphoSys. The mapping highly exploits ray-tracing parallelism. A straightforward mechanism is used to handle irregularity among parallel rays in BSP. To support this mechanism, a special data structure is established, in which no intermediate data has to be saved. Moreover, optimizations such as object reordering and merging are facilitated. Data starvation is avoided by overlapping data transfer with intensive computation so that applications with different complexity can be managed efficiently. Since MorphoSys is small in size and power efficient, we demonstrate that MorphoSys is an economic platform for 3D animation applications on portable devices.

Técnicas de processamento paralelo para sistemas gráficos de alto desempenho

Este artigo descreve as principais tecnicas de processamento paralelo empregadas na geracâo de im... more Este artigo descreve as principais tecnicas de processamento paralelo empregadas na geracâo de imagens por computador e apresenta as arquiteturas de alguns sistemas de visualizacâo de alto desempenho. Inicialmente este artigo analisa os problemas envolvidos na geracâo de imagens, de forma qualitativa e quantitativa. Em seguida e apresentada uma taxonomia de sistemas de geracâo de imagens, discutindo as principais vantagens e restricoes de cada um.