Papers by Mónico Linares Aranda
Analysis of On-Silicon-Vias for an Advanced RF-CMOS Process: Experimental Characterization and Modeling
2021 18th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)
In this work, a circuit model for interconnection channels with vertical inter-metallic transitio... more In this work, a circuit model for interconnection channels with vertical inter-metallic transitions based on the experimental characterization is proposed. The circuit model and extraction methodology was verified using a daisy chain structure manufactured in a 180 nm RF-CMOS process. Both, the parameters extraction methodology and the circuit model were considered for their use in RF applications, whereby they take into account the electromagnetic effects of high frequency. The obtained results show that the proposed circuit model has a maximum average error of 5.06% in magnitude when it is compared with experimental data.
Electromagnetic analysis of via arrays for different RF-CMOS technological nodes
2019 16th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE), 2019
With the scaling trend, the newer technologies have increased the size and number of metal layers... more With the scaling trend, the newer technologies have increased the size and number of metal layers to compensate the high integration density in the design of integrated circuits (ICs). The interconnections in the CMOS process have evolved from simple geometries to complex topologies with several thickness in its metal layers, intermetallic connections (vias) with different transversal areas and groups of dielectric materials between each metal layer. The interconnections in the IC introduces parasitic elements which depends of the designed IC and its operation frequency. In this work, we focused in the analysis of via arrays parasitic elements for high frequency applications. An electromagnetic (EM) analysis in different technologies was performed by using simulated 3D models of the via arrays extracted from a full wave solver with the objective to see the performance of the via arrays under high frequency effects. The results show that by increasing the connection area in the vertical interconnections not lead to lower parasitic behavior due to the inductive characteristic present in these interconnections at high frequency ranges.
A Test IC for Wafer-Level Characterization of an IntraCMOS-MEMS Fabrication Process
IEEE Latin America Transactions, 2022
Monitoring of fabrication processes and the measurement of the electrical and mechanical properti... more Monitoring of fabrication processes and the measurement of the electrical and mechanical properties of materials and devices at the silicon-wafer level are of vital importance on integrated system technologies. In this work, a test integrated circuit (IC) for the development of an IntraCMOS-MEMS fabrication process is presented. The test devices contained in the test IC are designed in such a way that 1) they can be used in CMOS-MEMS fabrication technologies using different materials, 2) take into account the capabilities of the manufacturing infrastructure, and 3) consider the selected integrated fabrication scheme; thus, any monolithic CMOS-MEMS process can be evaluated before, during and after the fabrication. The acquired data from the test devices will be useful to identify possible electrical and/or mechanical variations, in the properties of the materials used and in the performance characteristics of the devices, due to the fabrication process. The information acquired will help to adjust the simulation routines and the analytical modeling expressions. Finally, using the infrastructure of the MEMS Innovation Laboratory (LIMEMS-INAOE Mexico) preliminary experimental results are presented.
Anisotropic silicon etch to house CMOS compatible MEMS microstructures without planarization techniques
2017 14th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE), 2017
The MEMS (Micro-Electro-Mechanical Systems) acronym recalls mechanical structures of micrometric ... more The MEMS (Micro-Electro-Mechanical Systems) acronym recalls mechanical structures of micrometric dimensions performing a well-controlled electronically preset function. The real sense of a microelectromechanical system (MEMS) is the interaction of electronic circuits with the mechanical transducers (microstructures) to perform a useful function. However, the MEMS-microstructures require a wide range of thickness according to the particular application, and the resulting topography directly affects the subsequent photolithography steps. Fabrication of a trench as deep as the microstructures thickness using two solutions: TMAH (tetramethyl ammonium hydroxide) and KOH (potassium hydroxide), without the use of planarization techniques is presented. Inside the trench, the microstructures can be fabricated to obtain reliable microelectromechanical systems. It is shown that using TMAH solution the geometries can be placed at the edge of the trench with a good resolution and consistency. Th...
A simple model of inter-metallic connections (vias) in CMOS resonant rotary traveling wave oscillator (RTWO)
2017 14th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE), 2017
In this work, a simple electric circuit model for the evaluation of the impact of vias (inter-met... more In this work, a simple electric circuit model for the evaluation of the impact of vias (inter-metallic vertical connections) in resonant rotary traveling wave oscillator (RTWO) is proposed. A test structure was designed to quantify the degradation on the signal integrity of RTWOs caused by these vias. The test structure and the RTWO were designed according to the rules of the 130 nm commercial mixed mode, Single-Poly 8-Metal (1P8M), P-substrate, RFCMOS technology. The vias test structure consist of vertical inter-metallic connections and respective metallic pads. According to the used technology, the test structure was implemented using copper for all the metals layers. Simulations were performed using advanced tools: a 3D electromagnetic simulator (EMpro) for the extraction of the electrical properties of the test structure, HSPICE for electrical simulation and Mentor Graphics IC Studio for the geometric pattern (layout) design of the test structure. Finally, a 26.87 GHz RTWO was designed to quantify the performance of the oscillator under the effect of the vias.
Efecto de Discontinuidadesde Interconexiones en Osciladores No-Convencionales utilizando Tecnologías CMOS Nanométricas
En este trabajo se muestra el impacto de los efectos indeseados de discontinuidades de vias prese... more En este trabajo se muestra el impacto de los efectos indeseados de discontinuidades de vias presentes entre interconexiones durante el diseno de osciladores resonantes construidos en base a lineas de transmision. Los resultados de simulacion realizados, utilizando el programa HFSS (High Frequency Structural Simulator) y Mentor Graphics para diferentes tecnologias: 350, 180 y 130 nm; muestran que los efectos indeseados de interconexiones influyen en el funcionamiento de los osciladores y por lo tanto en el desempeno de redes de generacion y distribucion de senales a alta frecuencia utilizadas en la temporizacion y sincronizacion de circuitos integrados CMOS.
An analysis of on-silicon-via stacks in RF-CMOS processes
2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS), 2018
On-silicon vias (OSV) have always been present in any manufacturing process of integrated circuit... more On-silicon vias (OSV) have always been present in any manufacturing process of integrated circuits (IC) and its effect has been neglected (due to its size) in most applications. However, with the growing use of high frequency free bands, the effect from OSVs can have a significant impact on signal integrity. In this work, an analysis of several on-silicon via stacks and arrangements, built using two mixed mode RF-CMOS technologies, is carried out in order to quantify the frequency effects that changes the distribution of the current on interconnections. The on-silicon via arrangements and stacks were analyzed using a 3D electromagnetic (EM) simulation, and the results show that the effects of current redistribution increase for larger stacks and smaller OSVs in the low metal levels. It was observed that for the analyzed stacks, there is a reduction of the number of vias with current and this reduction can be up to 46.8 % depending of the frequency and the vias geometry.
Computación y Sistemas, 2011
This paper presents two new high-speed low-power 1-bit full-adder cells using an alternative logi... more This paper presents two new high-speed low-power 1-bit full-adder cells using an alternative logic structure, and the logic styles DPL and SR-CPL. The adders were designed using electrical parameters of a 0.35µm Complementary Metal-Oxide-Semiconductor (CMOS) process, and were compared with various adders published previously, with regards of power-delay product. To validate the performance simulation results of one of the proposed adders, an 8-bits pipelined multiplier was fabricated using a 0.35µm CMOS technology, and it showed to provide superior performance.
Una comparación de estilos lógicos de circuitos totalmente dinámicos
Topology and discontinuities effect on CMOS rotary traveling wave oscillators
2017 14th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE), 2017
In this paper, the effects of geometrical discontinuities and topological structure on Rotary Tra... more In this paper, the effects of geometrical discontinuities and topological structure on Rotary Travelling Wave Oscillators (RTWO) are studied. Using the 3D electromagnetic simulator EMPro Simulation Software Design Platform, we have found that reducing the corner discontinuities can increase the oscillation frequency up to 3.34%. Additionally, we observed that the topological structure of the RTWO affects also the different performance parameters, since as more folds and overlaps between metallic levels present the structure, the oscillation frequency is reduced and the power consumption of the RTWO resonator is increased.
Circuits, Systems, and Signal Processing, 2018
A semiempirical, piecewise-defined, and physical model for integrated circuit interconnects is pr... more A semiempirical, piecewise-defined, and physical model for integrated circuit interconnects is presented. The proposed model accurately represents the corresponding frequency-dependent resistance, and self-and mutual inductances while also accounting for the eddy currents induced in the ground metal layer. For the model implementation, different frequency regions where the resistance, and the self-and mutual inductances exhibit different trends due to the variation in the effective area where the current is flowing are identified, as well as the corresponding transitional frequencies. Experimental results performed to on-chip test structures fabricated on an RF-CMOS technology are used to validate the proposed model up to 40 GHz.
Solid-State Electronics, 2016
A physically-based piecewise modeling of the frequency-dependent series resistance and inductance... more A physically-based piecewise modeling of the frequency-dependent series resistance and inductance of IC interconnects is presented. The model relies on representing the influence of the frequency-dependent skin and current distribution effects on the characteristics of the interconnects, and detailed explanation of the model parameter extraction is also given. This modeling allows to accurately represent the high-frequency performance of on-chip interconnects by considering the correct and physically expected variation of the series resistance and inductance with frequency. Results in the frequency domain show excellent model-experiment correlations for interconnects fabricated on RF-CMOS technology. Moreover, time domain results were also performed to demonstrate the causality of the proposed model.
DOAJ (DOAJ: Directory of Open Access Journals), Sep 27, 2010
Actualmente el diseño de sistemas de generación y distribución de señal/es de reloj de alto desem... more Actualmente el diseño de sistemas de generación y distribución de señal/es de reloj de alto desempeño (alta frecuencia, skew, jitter y consumo de potencia reducidos) para sistemas en un Solo Chip (SoC), constituye una importante área de investigación en el desarrollo de sistemas electrónicos. En este artículo se presenta un análisis de las principales filosofías de diseño de redes de generación y distribución de señal de reloj actuales y futuras. Se deriva que las redes no-resonantes en base a osciladores controlados por voltaje/corriente representan una alternativa altamente atractiva para la sincronización de sistemas en un solo chip debido a su fácil diseño, alta regularidad, y escalabilidad con la tecnología de fabricación.
Science Journal of Circuits, Systems and Signal Processing, 2013
In this work, a performance comparison of expanded CMOS voltage-controlled ring oscillators for n... more In this work, a performance comparison of expanded CMOS voltage-controlled ring oscillators for non-resonant local clock generation and distribution networks is presented. Several differential and single-ended ring oscillators are designed and fabricated using long interconnection lines to achieve wide coverage chip. A test chip containing the several oscillators was fabricated using an Austria Microsystems (AMS) 0.35 µm CMOS technology. Experimental results show that it is possible to generate and distribute high frequency signals (GHz range) on a relativity large area (coverage) and low phase noise using non-resonant ring oscillators. This represents an attractive alternative for the design and implementation of local Clock Generation and Distribution Networks for systems on chip.
An architecture for fractal image compression using quad-tree multiresolution
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)
... In order to reduce the number of operations involved in fractal codification, it has been com... more ... In order to reduce the number of operations involved in fractal codification, it has been commonly used the local search for similarity between range and domain blocks, with a (2L+1)×(2L+1) window of domain blocks, centered on the range block to be codified, where 0L<(NR/2 ...
An Alternative Logic Approach to Implement High-Speed Low-Power Full Adder Cells
2005 18th Symposium on Integrated Circuits and Systems Design, 2005
... adder designed using DPL logic style to build the XOR/XNOR gates and a pass-transistor based ... more ... adder designed using DPL logic style to build the XOR/XNOR gates and a pass-transistor based multiplexer to obtain the So output. In Figure 4, the SR-CPL logic style was used instead to build these gates. In both cases, the AND/OR gates have been built using a powerless ...
Study of on-chip vias of resonant rotary traveling wave oscillators
2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC), 2014
The accelerated increment of operation frequencies in integrated circuits (ICs) in sub-micron tec... more The accelerated increment of operation frequencies in integrated circuits (ICs) in sub-micron technologies above GHz, makes that conventional clock signal distribution networks (H and X trees, spine, etc.) become obsolete due to the large number of lines and buffers that conform them, making them to have a high power consumption as well as high uncertainty time in the arrival of the clock signals to the sinks (registers, gates, blocks, etc.). Therefore, there have been sought alternatives capable to distribute clock signals with a reduced power consumption and minimum uncertainty in time (skew and jitter). The resonant networks are an excellent choice, since they take advantage of the parasitic elements (capacitances and inductances) present in transmission lines to generate oscillations, whereby, they are able to distribute clock signals at the same time that generate them; this causes the power consumption in these structures is less than for conventional networks [1]. One of the most promising resonant structure is the Rotary Traveling Wave Oscillator (RTWO), which is formed by a closed loop and a mobius termination to recirculate the energy as shown in [2]. Although these resonant structures have been extensively studied in recent years, few papers like [3] have focused on study the impact of the different physical shapes of these networks, such as the folds of the resonant ring, the spacing between lines that transport the signal (odd mode differential transmission lines), and the widths thereof.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03, 2003
The performance of interconnected rings and oscillators, working as clock distribution networks, ... more The performance of interconnected rings and oscillators, working as clock distribution networks, is analyzed and compared among several configurations. The use of interconnected 3-inverter rings as globally asynchronous, locally synchronous clock distribution networks is proposed even for chip lengths from 4 to 24 mm. In this approach, modularity and basic cell properties are kept while the power consumption results directly proportional to the number of blocks. Typical 3.3V AMS 0.35µm CMOS N-well process parameters were used for the analysis. Regarding the current area expansion, we show that interconnected rings is a more robust approach than the interconnected oscillators.
Effect of changing the material and device's properties on the performance of polysilicon-based MicroActuators
2013 10th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE), 2013
ABSTRACT In this paper, the performance of polysilicon electrothermal actuators (Chevron-type, fa... more ABSTRACT In this paper, the performance of polysilicon electrothermal actuators (Chevron-type, fabricated with the PolyMEMS-INAOE® technology) when the material properties and device geometry are varied, is analyzed. These micro-actuators operating under Joule heating can generate a mechanical displacements ranging in a few tens of micrometers. These devices can delivering a mechanical force in the range of milliNewtons (mN) and are very attractive due to high efficient mechanical response and fully compatible with standard integrated silicon circuitry. Based on analytical and simulation models, the overall mechanical performance was analyzed when some of the polysilicon properties were varied. During the electrothermal performance, the mechanical displacement was experimentally measured. Comparing simulated, analytical and experimental approaches, a good phenomenological agreement is confirmed.
Hybrid adders for high-speed arithmetic circuits: A comparison
2010 7th International Conference on Electrical Engineering Computing Science and Automatic Control, 2010
... 371-376, 2008. [11] K. Navi, M. Reza Saatchi, O. Daei, A High-speed hybrid full adder, Euro... more ... 371-376, 2008. [11] K. Navi, M. Reza Saatchi, O. Daei, A High-speed hybrid full adder, European Journal of Scientific Research, vol. 26, no. 1, pp. 29-33, 2009. [12] Ilham Hassoune1, Amaury Neve, Jean-Didier Legat, and Denis Flandre. ...
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Papers by Mónico Linares Aranda