Papers by Liudmila Cheremisinova
The problem of preparation of a program to perform it on multiprocessor system of a cluster type ... more The problem of preparation of a program to perform it on multiprocessor system of a cluster type is considered. When developing programs for a cluster computer the technology based on use of the remote terminal is applied. The situation when such remote terminal is the computer with operational system Windows is considered. The set of the tool means, allowing carrying out of editing program texts, compiling and starting programs on a cluster computer, is suggested. Advantage of an offered way of preparation of programs to execution is that it allows as much as possible to use practical experience of programmers used to working in OS Windows environment.
Pattern Recognition and Image Analysis, 2020
The paper presents a computer program for automatically extracting the hierarchy of a large-scale... more The paper presents a computer program for automatically extracting the hierarchy of a large-scale digital circuit from its transistor-level description derived from the layout of VLSI circuit. The considered problem arises in VLSI layout verification as well as in the circuit reengineering. The proposed subcircuit recognition algorithm extracts functional level structure from transistor-level circuit collecting transistors into gates without using any predefined cell library. The algorithm comes from a SPICE like network description and realizes three-step process. First, a structural approach in which gate structures are recognized as channel connected sequences of transistors is used. Then channel connected sequences of transistors which implement CMOS gates are searched for. And finally the method of subcircuit pattern recognition is used to gather the rest sequences of transistors into minimal number of classes of identical functional blocks. The presented algorithm has been implemented as a program in C++ and tested using practical transistor-level circuits.
Russian Microelectronics, 2019
In this paper, we address the problem of converting a flat CMOS circuit of transistors in the SPI... more In this paper, we address the problem of converting a flat CMOS circuit of transistors in the SPICE format into a hierarchical circuit of CMOS gates in the same format. This problem arises in the process of layout versus schematic (LVS) verification, as well as when reengineering integrated circuits. A method for recognizing subcircuits (CMOS gates) is described. The method is implemented as a C++ program; it recognizes subcircuits that are described by the same logic functions but are not isomorphic at the transistor level as different ones. This provides the isomorphism of the original and decompiled circuits.
Russian Microelectronics, 2018
⎯We describe a CMOSLD system to automate the design of irregular logic circuits of CMOS library e... more ⎯We describe a CMOSLD system to automate the design of irregular logic circuits of CMOS library elements. The main criteria of circuits optimization are the area and the power consumption. This system is integrated with software packages Questa Sim, LeonardoSpectrum, and Accusim II (Mentor Graphics). This makes it possible to perform efficiently logical simulation, synthesis, resynthesis and estimation of energy consumption based on logical and circuit simulation.
This paper presents some results of PLA area optimizing by means of its column and row folding. A... more This paper presents some results of PLA area optimizing by means of its column and row folding. A more restricted type of PLA simple folding is considered. It is introduced by Egan and Liu and called as bipartite folding. An efficient approach is presented which allows finding an optimal bipartite folding without exhaustive computational efforts.
Design of Embedded Control Systems
ABSTRACT A problem of race-free state assignment of asynchronous parallel automata is considered.... more ABSTRACT A problem of race-free state assignment of asynchronous parallel automata is considered. The goal is to encode partial states of parallel automaton using minimal number of coding variables and excluding critical races during automaton operation. Requirements imposing on the partial states codes to eliminate the in-fluence of races are formulated. An exact algorithm to find a minimal solution of the problem of race-free state assignment for parallel automata is suggested. The algorithm provides reducing the computational efforts when searching for state encoding.
East-West Design & Test Symposium (EWDTS 2013), 2013
An approach to logic synthesis using CMOC element library is suggested, which allows to minimize ... more An approach to logic synthesis using CMOC element library is suggested, which allows to minimize the area and the average value of the dissipated power of microcircuit implemented on CMOC VLSI chip. The case of synthesis of combinational CMOC networks is considered when key schematic solutions, such as clock frequency and supply voltage, are assigned, and for the purposes of energy estimation during the synthesis process the static method based on probabilistic properties of input signals is used. The synthesis is comprised of the technology independent phase where logic minimization and decomposition is performed on the Boolean functions equations and the technology dependent phase where mapping to a physical cell library is performed.
Automatic Control and Computer Sciences, 2010
The verification problem for the case of the description of a functional indeterminacy set by a s... more The verification problem for the case of the description of a functional indeterminacy set by a system of partially specified Boolean functions is considered. The formal approach based on the reduction of the verification problem to a satisfiability test of the conjunctive normal form is suggested. Three approaches to the solution of the verification problem based on sequential, simultaneous, and group testing of multi output intervals of the system of partially specified Boolean functions are inves tigated.
2010 East-West Design & Test Symposium (EWDTS), 2010
Abstract The problem under discussion is to check whether a given combinational network implement... more Abstract The problem under discussion is to check whether a given combinational network implements a system of incompletely specified Boolean functions. SAT-based procedure is discussed that formulates the overall problem as conventional conjunctive normal form ( ...
An approach to logic synthesis using CMOS element library is suggested, it allows to minimize the... more An approach to logic synthesis using CMOS element library is suggested, it allows to minimize the area and the average value of power consumption of microcircuit implemented on CMOS VLSI chip. The case of synthesis of combinational CMOS networks is considered when, for the purposes of energy estimation during the synthesis process, the static method based on probabilistic properties of input signals is used. The synthesis is comprised of the technology independent phase where logic minimization and decomposition are performed on the Boolean functions equations and the technology dependent phase where mapping to a physical cell library is performed.
IJ ITA is official publisher of the scientific papers of the members of the ITHEA ® International... more IJ ITA is official publisher of the scientific papers of the members of the ITHEA ® International Scientific Society IJ ITA welcomes scientific papers connected with any information theory or its application. IJ ITA rules for preparing the manuscripts are compulsory. The rules for the papers for IJ ITA as well as the subscription fees are given on www.ithea.org. The camera-ready copy of the paper should be received by http://ij.ithea.org. Responsibility for papers published in IJ ITA belongs to authors. General Sponsor of IJ ITA is the Consortium FOI Bulgaria (www.foibg.com). Abstract: The purpose of the paper is to explore the possibility of applying the language PRALU, proposed for description of parallel logical control algorithms and rooted in the Petri net formalism for design and modeling real-time multi-agent systems. It is demonstrated with a known example of English auction on how to specify an agent interaction protocol using considered means. A methodology of programming ...
The purpose of the paper is to explore the possibility of applying existing formal theories of de... more The purpose of the paper is to explore the possibility of applying existing formal theories of description and design of distributed and concurrent systems to interaction protocols for real-time multi-agent systems. In particular it is shown how the language PRALU, proposed for description of parallel logical control algorithms and rooted in the Petri net formalism, can be used for the modeling of complex concurrent conversations between agents in a multi-agent system. It is demonstrated with a known example of English auction on how to specify an agent interaction protocol using considered means.
The problem of mapping a concurrent control algorithm onto a program structure for Programmable L... more The problem of mapping a concurrent control algorithm onto a program structure for Programmable Logic Controller is discussed. The systematic method to derive Ladder Diagram programs from a parallel automaton that is a functional model of logic control device is presented. The mapping process is decomposed into a sequence of optimizing transformations of mathematical models of a parallel control algorithm specified in a formal language PRALU. The suggested procedures of optimizing the mathematical models are based on providing the proper control for a specific object under the control, i.e. within the restricted domain.
book maintains articles on actual problems of research and application of information technologie... more book maintains articles on actual problems of research and application of information technologies, especially the new approaches, models, algorithms and methods fot information modeling of knowledge in: Intelligence metasynthesis and knowledge processing in intelligent systems; Formalisms and methods of knowledge representation; Connectionism and neural nets; System analysis and sintesis; Modelling of the complex artificial systems; Image Processing and Computer Vision; Computer virtual reality; Virtual laboratories for computer-aided design; Decision support systems; Information models of knowledge of and for education; Open social info-educational
Abstract: The problem under discussion is to check whether a given combinational network realizes... more Abstract: The problem under discussion is to check whether a given combinational network realizes a system of incompletely specified Boolean functions. SAT-based procedure is discussed that formulates the overall problem as conventional conjunctive normal form (CNF) on the basis of encoding of multiple-output cubes the Boolean functions are specified on and checking whether the combinational network realizes them using a SAT solver. The novel method is proposed that speeds up the SAT-based procedure due to suggested efficient procedure of logarithmic encoding multiple-output cubes that allows reducing the number of variables to be additionally introduced into the CNF under construction.
The problem under consideration is to find a synchronizing sequence for a logic network with memo... more The problem under consideration is to find a synchronizing sequence for a logic network with memory. A novel method is proposed that is based on formulation of the task as the Boolean satisfiability problem solved with any standard SAT solver. The developed method allows creating a Boolean equation presenting the problem in conjunctive normal form.
Abstract. The purpose of the paper is to explore the possibility of applying existing formal theo... more Abstract. The purpose of the paper is to explore the possibility of applying existing formal theories of description and design of distributed and concurrent systems to interaction protocols for real-time multi-agent systems. In particular it is shown how the language PRALU, proposed for description of parallel logical control algorithms and rooted in the Petri net formalism, can be used for the modeling of complex concurrent conversations between agents in a multi-agent system. It is demonstrated with a known example of English auction on how to specify an agent interaction protocol using considered means.
Abstract: A verification task of proving the equivalence of two descriptions of the same device i... more Abstract: A verification task of proving the equivalence of two descriptions of the same device is examined for the case, when one of the descriptions is partially defined. In this case, the verification task is reduced to checking out whether logical descriptions are equivalent on the domain of the incompletely defined one. Simulation-based approach to solving this task for different vector forms of description representations is proposed. Fast Boolean computations over Boolean and ternary vectors having big sizes underlie the offered methods.
Abstract. The problem of checking whether a system of incompletely specified Boolean functions is... more Abstract. The problem of checking whether a system of incompletely specified Boolean functions is implemented by the given combinational circuit is considered. The task is reduced to testing out if two given logical descriptions are equivalent on the domain of one of them having functional indeterminacy. We present a novel SAT-based verification method that is used for testing whether the given circuit satisfies all the conditions represented by the system of incompletely specified Boolean functions.
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Papers by Liudmila Cheremisinova