We present an approach to process scheduling based on an abstract graph representation which capt... more We present an approach to process scheduling based on an abstract graph representation which captures both dataflow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.
Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition
This paper presents an approach for system level specification and hardware/software partitioning... more This paper presents an approach for system level specification and hardware/software partitioning with VHDL. The implications of using VHDL as a specification language are discussed and a message passing mechanism is proposed for process interaction. We define the metric values for partitioning and develop a cost function that guides our heuristics towards performance optimization under hardware and software cost constraints. Experimental results are presented. This work has been partially sponsored by the Swedish National Board for Industrial and Technical Development (NUTEK). 2. The co-synthesis environment An overview of our hardware/software co-synthesis environment is depicted in Fig. 1. The input specification describes system functionality in terms of interacting processes modeled in VHDL which has been extended with a message passing mechanism for interprocess communication. When the final partitioning is done, the hardware implementation is synthesized by the CAMAD high-level synthesis (HLS) system [17] while the software is generated
How constrains programming can help you in the generation of optimized application specific reconfigurable processor extensions
A regulator for a polyphase alternator for a motor vehicle, the regulator including detector mean... more A regulator for a polyphase alternator for a motor vehicle, the regulator including detector means for detecting a voltage difference between the phase terminals of said alternator, which comprise at least one transistor circuit forming a current mirror whose two branches are connected at one end to respective ones of the two phase terminals and are connected at the other end to transistors forming current sources that supply said branches with currents of the same magnitude, those branches also having resistors of different resistances such that one of the transistors becomes non-conductive when a voltage difference in excess of a given threshold appears between the two phase terminals, said transistor becoming non-conductive giving rise to a change in the level of a logic output controlled by the voltage at a point on said branch between the current source transistor and the current mirror transistor.
1993 European Conference on Design Automation with the European Event in ASIC Design
This paper presents a simulated-annealing based algorithm to partition an application specific sy... more This paper presents a simulated-annealing based algorithm to partition an application specific system into a set of modules. The role of partitioning is to discover the structure implicit in the functional specification of the system so as to guide high level synthesis decisions in a design environment for digital systems consisting of hardware parts and possibly software components. The partitioning algorithm can also be used to partition the final or intermediate results of a high-level synthesis process into several physical blocks. Experimental results show that our approach produces better register-transfer designs with less global communications. This work has been supported by the Swedish National Board for Industrial and Technical Development (NUTEK).
Proceedings of 9th International Symposium on Systems Synthesis
The paper presents two heuristics for hardwarelsoftware partitioning of system level spec@cations... more The paper presents two heuristics for hardwarelsoftware partitioning of system level spec@cations. The main objective is to achieve pedormance optimization with a limited hardware and software cost. We consider minimization of communication cost and improvement of the overall parallelism as essential criteria. One ofthe heuristics is based on simulated annealing and the other on tabu search. Experiments show the superiority of the tabu search based algorithm.
In this chapter several issues concerning system-level synthesis starting from VHDL specification... more In this chapter several issues concerning system-level synthesis starting from VHDL specifications are discussed. We concentrate here on aspects which are characteristic to the synthesis of hardware components. Specifications containing subprograms and interacting processes are of main interest in this context. The last section is devoted to the problem of specifying timing constraints and of hardware synthesis under restrictions imposed by such constraints.
Proceedings EURO-DAC '92: European Design Automation Conference
This paper presents an approach to use VHDL as input specijicatwn to the CAIUAD high-level synthe... more This paper presents an approach to use VHDL as input specijicatwn to the CAIUAD high-level synthesis system. In particular, it describes a synthesis-oriented compiler which takes a subset of VHDL as input and compiles it into the internal &sign representatwn of CAiUAD, which can then be synthesized into register-transfer level &sign. Since CAMAD supports the &sign of hardware with concurrency and asynchrony, our VHDL subset includes the concurrent features of the language. We present also in the paper some important concl~"ons concerning how to deal with signals, want statements, structured a%ta, and subprograms.
This paper describes a method to implement restricted timed Petri nets by microprograms. These ti... more This paper describes a method to implement restricted timed Petri nets by microprograms. These timed Petri nets are used to represent control parts of VLSI systems to produce sequences of control signals that evoke the operations of a corresponding data part. The proposed method consists of a set of transformation algorithms which have been implemented as parts of CAMAD, an integrated design aid system. We have also studied the problem of microprogram optimization, for example, how to reconstruct the control structure of a VLSI system so as to produce better microprograms.
We present an approach to process scheduling based on an abstract graph representation which capt... more We present an approach to process scheduling based on an abstract graph representation which captures both dataflow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.
Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition
This paper presents an approach for system level specification and hardware/software partitioning... more This paper presents an approach for system level specification and hardware/software partitioning with VHDL. The implications of using VHDL as a specification language are discussed and a message passing mechanism is proposed for process interaction. We define the metric values for partitioning and develop a cost function that guides our heuristics towards performance optimization under hardware and software cost constraints. Experimental results are presented. This work has been partially sponsored by the Swedish National Board for Industrial and Technical Development (NUTEK). 2. The co-synthesis environment An overview of our hardware/software co-synthesis environment is depicted in Fig. 1. The input specification describes system functionality in terms of interacting processes modeled in VHDL which has been extended with a message passing mechanism for interprocess communication. When the final partitioning is done, the hardware implementation is synthesized by the CAMAD high-level synthesis (HLS) system [17] while the software is generated
How constrains programming can help you in the generation of optimized application specific reconfigurable processor extensions
A regulator for a polyphase alternator for a motor vehicle, the regulator including detector mean... more A regulator for a polyphase alternator for a motor vehicle, the regulator including detector means for detecting a voltage difference between the phase terminals of said alternator, which comprise at least one transistor circuit forming a current mirror whose two branches are connected at one end to respective ones of the two phase terminals and are connected at the other end to transistors forming current sources that supply said branches with currents of the same magnitude, those branches also having resistors of different resistances such that one of the transistors becomes non-conductive when a voltage difference in excess of a given threshold appears between the two phase terminals, said transistor becoming non-conductive giving rise to a change in the level of a logic output controlled by the voltage at a point on said branch between the current source transistor and the current mirror transistor.
1993 European Conference on Design Automation with the European Event in ASIC Design
This paper presents a simulated-annealing based algorithm to partition an application specific sy... more This paper presents a simulated-annealing based algorithm to partition an application specific system into a set of modules. The role of partitioning is to discover the structure implicit in the functional specification of the system so as to guide high level synthesis decisions in a design environment for digital systems consisting of hardware parts and possibly software components. The partitioning algorithm can also be used to partition the final or intermediate results of a high-level synthesis process into several physical blocks. Experimental results show that our approach produces better register-transfer designs with less global communications. This work has been supported by the Swedish National Board for Industrial and Technical Development (NUTEK).
Proceedings of 9th International Symposium on Systems Synthesis
The paper presents two heuristics for hardwarelsoftware partitioning of system level spec@cations... more The paper presents two heuristics for hardwarelsoftware partitioning of system level spec@cations. The main objective is to achieve pedormance optimization with a limited hardware and software cost. We consider minimization of communication cost and improvement of the overall parallelism as essential criteria. One ofthe heuristics is based on simulated annealing and the other on tabu search. Experiments show the superiority of the tabu search based algorithm.
In this chapter several issues concerning system-level synthesis starting from VHDL specification... more In this chapter several issues concerning system-level synthesis starting from VHDL specifications are discussed. We concentrate here on aspects which are characteristic to the synthesis of hardware components. Specifications containing subprograms and interacting processes are of main interest in this context. The last section is devoted to the problem of specifying timing constraints and of hardware synthesis under restrictions imposed by such constraints.
Proceedings EURO-DAC '92: European Design Automation Conference
This paper presents an approach to use VHDL as input specijicatwn to the CAIUAD high-level synthe... more This paper presents an approach to use VHDL as input specijicatwn to the CAIUAD high-level synthesis system. In particular, it describes a synthesis-oriented compiler which takes a subset of VHDL as input and compiles it into the internal &sign representatwn of CAiUAD, which can then be synthesized into register-transfer level &sign. Since CAMAD supports the &sign of hardware with concurrency and asynchrony, our VHDL subset includes the concurrent features of the language. We present also in the paper some important concl~"ons concerning how to deal with signals, want statements, structured a%ta, and subprograms.
This paper describes a method to implement restricted timed Petri nets by microprograms. These ti... more This paper describes a method to implement restricted timed Petri nets by microprograms. These timed Petri nets are used to represent control parts of VLSI systems to produce sequences of control signals that evoke the operations of a corresponding data part. The proposed method consists of a set of transformation algorithms which have been implemented as parts of CAMAD, an integrated design aid system. We have also studied the problem of microprogram optimization, for example, how to reconstruct the control structure of a VLSI system so as to produce better microprograms.
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Papers by K. Kuchcinski