Multiple experts system is shown to be a promising strategy for handwritten recognition. This pap... more Multiple experts system is shown to be a promising strategy for handwritten recognition. This paper presents a multiple experts system using neural networks. In the proposed system, the authors have developed: (1) an incremental clustering neural network algorithm with merging and canceling process, (2) a modified directional histogram feature extraction method, and (3) a subclass method with learning rejection neuron strategy. Our experimental results on a large set of data show the efficiency and robustness of the proposed system.
This paper presents a hierarchical neural network architecture for recognition of handwritten num... more This paper presents a hierarchical neural network architecture for recognition of handwritten numeral characters. In this new architecture, two separately trained neural networks connected in series, use the pixels of the numeral image as input and yield ten outputs, the largest of which identifies the class to which the numeral image belongs. The first neural network generates the principal components of the numeral image using Oja's rule, while the second neural network uses an unsupervised learning strategy to group the principal components into distinct character clusters. In this scheme, there is more than one cluster for each numeral class. The decomposition of the global network into two independent neural networks facilitates rapid and efficient training of the individual neural networks. Results obtained with a large independently generated data set indicate the effectiveness of the proposed architecture.
The Synchronous Optical Network (SONET) protocol is the stan-dard for specifying components in op... more The Synchronous Optical Network (SONET) protocol is the stan-dard for specifying components in optical communications sys-tems used in WANs [1]. The next generation of fiber-optic com-munications systems to be deployed runs at the OC-192 rate, ~10Gb/s. ...
The convergence of various data communication technologies into the gigabit domain has directed t... more The convergence of various data communication technologies into the gigabit domain has directed the efforts of IC designers developing high-speed, low-power, low-cost, highly integrated circuits for broadband signals. This fully integrated OC-192 receiver in standard 0.18µm CMOS ...
AbstractA 16-b 2.5-MHz output-rate analog-to-digital converter (ADC) for wireline communications... more AbstractA 16-b 2.5-MHz output-rate analog-to-digital converter (ADC) for wireline communications and high-speed in-strumentation has been developed. A 2-1-1 cascaded deltasigma modulator (DSM) employing 4-b quantizers in every stage makes all quantization noise sources ...
This paper presents the first fully integrated, SONET OC-48 (2.488/2.666 Gb/s) transceiver using ... more This paper presents the first fully integrated, SONET OC-48 (2.488/2.666 Gb/s) transceiver using a standard CMOS process. Careful design methodology combined with a standard CMOS technology allows performance exceeding SONET requirements with the added benefits of reduced power dissipation, higher integration levels, and simplified manufacturability as compared to other fabrication technologies. This chip, designed using a standard 0.18-m CMOS technology, has a total power dissipation of 500 mW and an rms jitter of 1 ps.
Multiple experts system is shown to be a promising strategy for handwritten recognition. This pap... more Multiple experts system is shown to be a promising strategy for handwritten recognition. This paper presents a multiple experts system using neural networks. In the proposed system, the authors have developed: (1) an incremental clustering neural network algorithm with merging and canceling process, (2) a modified directional histogram feature extraction method, and (3) a subclass method with learning rejection neuron strategy. Our experimental results on a large set of data show the efficiency and robustness of the proposed system.
This paper presents a hierarchical neural network architecture for recognition of handwritten num... more This paper presents a hierarchical neural network architecture for recognition of handwritten numeral characters. In this new architecture, two separately trained neural networks connected in series, use the pixels of the numeral image as input and yield ten outputs, the largest of which identifies the class to which the numeral image belongs. The first neural network generates the principal components of the numeral image using Oja's rule, while the second neural network uses an unsupervised learning strategy to group the principal components into distinct character clusters. In this scheme, there is more than one cluster for each numeral class. The decomposition of the global network into two independent neural networks facilitates rapid and efficient training of the individual neural networks. Results obtained with a large independently generated data set indicate the effectiveness of the proposed architecture.
The Synchronous Optical Network (SONET) protocol is the stan-dard for specifying components in op... more The Synchronous Optical Network (SONET) protocol is the stan-dard for specifying components in optical communications sys-tems used in WANs [1]. The next generation of fiber-optic com-munications systems to be deployed runs at the OC-192 rate, ~10Gb/s. ...
The convergence of various data communication technologies into the gigabit domain has directed t... more The convergence of various data communication technologies into the gigabit domain has directed the efforts of IC designers developing high-speed, low-power, low-cost, highly integrated circuits for broadband signals. This fully integrated OC-192 receiver in standard 0.18µm CMOS ...
AbstractA 16-b 2.5-MHz output-rate analog-to-digital converter (ADC) for wireline communications... more AbstractA 16-b 2.5-MHz output-rate analog-to-digital converter (ADC) for wireline communications and high-speed in-strumentation has been developed. A 2-1-1 cascaded deltasigma modulator (DSM) employing 4-b quantizers in every stage makes all quantization noise sources ...
This paper presents the first fully integrated, SONET OC-48 (2.488/2.666 Gb/s) transceiver using ... more This paper presents the first fully integrated, SONET OC-48 (2.488/2.666 Gb/s) transceiver using a standard CMOS process. Careful design methodology combined with a standard CMOS technology allows performance exceeding SONET requirements with the added benefits of reduced power dissipation, higher integration levels, and simplified manufacturability as compared to other fabrication technologies. This chip, designed using a standard 0.18-m CMOS technology, has a total power dissipation of 500 mW and an rms jitter of 1 ps.
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