S-sequence: a new floorplan representation method preserving room abutment relationships
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)
In this paper, we propose Segment-State Sequence (S-sequence), a new encoding method of floorplan... more In this paper, we propose Segment-State Sequence (S-sequence), a new encoding method of floorplans with different abutment relationships between rooms. The proposed method provides necessary and sufficient conditions to abut two modules facing to the same segment partitioning a floorplan, and an abutment judgment which checks whether pairs of modules abut on the floorplan or not by using S-sequence. Since our algorithm checks abutment relationships of the rooms before decoding, we need not decode an S-sequence which does not meet abutment constraints in a Simulated Annealing process. Consequently, we can optimize floorplans satisfying abutment constraints rapidly. In experiments, we implemented the floorplan optimization algorithm with S-sequence and the abutment judgment method, and the results show that the proposed algorithm optimized floorplan satisfies abutment constraints rapidly.
Transactions of Japanese Society for Medical and Biological Engineering, 2013
2 This paper introduces a tiny inner bladder pressure sensing system for long term ambulatory uro... more 2 This paper introduces a tiny inner bladder pressure sensing system for long term ambulatory urodynamic monitoring. In order to realize this system, a small System-on-a Chip (SoC) called Medical Domain Specific SOC, Type-I (MeSOC-I) has been developed. MeSOC-I enables an inner bladder pressure sensing system to conduct more than 72 hours measurement with a small battery.
Multi-Dimensional Parity Check (MDPC) code is an error correcting code which has been widely used... more Multi-Dimensional Parity Check (MDPC) code is an error correcting code which has been widely used for wireless communications under low error rate environment. In this study, a low-power processor for MDPC code processing is introduced and evaluated. Through experimental results, the proposed processor achieves about 90% lower in energy consumption compared with an implementation by a canonical RISC processor.
A low-energy ASIP with flexible exponential Golomb codec for lossless data compression toward artificial vision systems
2015 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2015
This paper proposes an application-domain specific instruction-set processor (ASIP) with dedicate... more This paper proposes an application-domain specific instruction-set processor (ASIP) with dedicated instructions for lossless data compression and decompression process to be used in artificial vision systems. Proposed ASIP has dedicated instructions to accelerate the performance to codec operations of Exponential Golomb coding, where the coding parameter value can be set by the user in order to maximize the compression ratio. Experimental results through simulation show that the proposed ASIP reduces execution cycles by 88% for compression and 42% for decompression, and reduces energy consumption by 85% for compression and 40% for decompression, compared with the base reduced instruction set computer processor.
A Block-Floating-Point Processor for Rapid Application Development
2007 IEEE International Conference on Acoustics, Speech and Signal Processing - ICASSP '07, 2007
This paper proposes an instruction set processor which uses hierarchical block-floating-point (H-... more This paper proposes an instruction set processor which uses hierarchical block-floating-point (H-BFP) arithmetic. H-BFP has been developed to provide efficient development approach for digital signal processing system. H-BFP offers highly abstracted computation model, and leads to cost-effective implementation. However, application development based on H-BFP is still time consuming task because of lacking high level programming language. In this paper, a processor architecture together with a set of instructions to support H-BFP are proposed. We also propose a related software development environment for efficient algorithm translation which generate high performance codes without any time consuming task. Experimental results show proposed environment achieves high performance signal processing systems with H-BFP processors.
In this paper, we propose a compiler generation method from architecture description language (AD... more In this paper, we propose a compiler generation method from architecture description language (ADL) of ASIP Integrated Development Environment. By using our proposed method the modification of compiler, due to changes in processor specification, becomes easier and the amount of description and design time can be reduced. In our experiments, we compared the description and design time of an ASIP using our proposed method and conventional method, which generates a compiler manually. The experimental results show that the proposed method can reduce both the amount of the description and the design time by approximately 80% as compared to conventional method.
Atsushi KISHIMOTO†, Nagisa ISHIURA††, Yuuki MASUI††, and Masaharu IMAI††† † Graduate School of Sc... more Atsushi KISHIMOTO†, Nagisa ISHIURA††, Yuuki MASUI††, and Masaharu IMAI††† † Graduate School of Science, Kwansei Gakuin University 2–1 Gakuen, Sanda, Hyogo, 669–1337, Japan †† Science and Technology, Kwansei Gakuin University 2–1 Gakuen, Sanda, Hyogo, 669–1337, Japan ††† Graduate School of Information Science and Technology, Osaka University 1–5 Yamadaoka, Suita, Osaka, 565–0871, Japan E-mail: †[email protected], ††{ishiura,bux65238}@ksc.kwansei.ac.jp, † † †[email protected]
This paper presents the methodology and the modeling constructs we have developed to capture the ... more This paper presents the methodology and the modeling constructs we have developed to capture the real time aspects of RTOS simulation models in a System Level Design Language (SLDL) like SystemC. We describe these constructs and show how they are used to build a simulation model of an RTOS kernel targeting the µ-ITRON OS specification standard.
This paper proposes a novel data compression method for artificial vision systems and its low-ene... more This paper proposes a novel data compression method for artificial vision systems and its low-energy implementation in order to reduce energy consumption in a wireless communication subsystem. The artificial vision systems are one of the methods for realizing visual prosthesis by controlling stimulus to visual nerves, and they consist of an inner stimulating unit and an outer image processing unit. The outer unit transmits information regarding stimulation to the inner unit via wireless communication, which occupies a large portion of the whole energy consumption. Reducing traffic in wireless communication is important to prevent damage caused by extra heat dissipation of the inner unit, which leads to excess energy consumption. The proposed compression method marks a higher compression ratio than the conventional compression methods by taking advantage of the analyses of stimuli position data, which is dominant in traffic. The proposed method is implemented as an application-domain specific instruction-set processor to achieve both configurability of stimulation control and compression efficiency. The evaluation results show that the proposed implementation reduces energy consumption by about 87% and 62% in the compression and decompression process, respectively. These results indicate that the proposed method can expect to reduce energy consumption in a wireless communication receiver dramatically.
S-sequence: a new floorplan representation method preserving room abutment relationships
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)
In this paper, we propose Segment-State Sequence (S-sequence), a new encoding method of floorplan... more In this paper, we propose Segment-State Sequence (S-sequence), a new encoding method of floorplans with different abutment relationships between rooms. The proposed method provides necessary and sufficient conditions to abut two modules facing to the same segment partitioning a floorplan, and an abutment judgment which checks whether pairs of modules abut on the floorplan or not by using S-sequence. Since our algorithm checks abutment relationships of the rooms before decoding, we need not decode an S-sequence which does not meet abutment constraints in a Simulated Annealing process. Consequently, we can optimize floorplans satisfying abutment constraints rapidly. In experiments, we implemented the floorplan optimization algorithm with S-sequence and the abutment judgment method, and the results show that the proposed algorithm optimized floorplan satisfies abutment constraints rapidly.
Transactions of Japanese Society for Medical and Biological Engineering, 2013
2 This paper introduces a tiny inner bladder pressure sensing system for long term ambulatory uro... more 2 This paper introduces a tiny inner bladder pressure sensing system for long term ambulatory urodynamic monitoring. In order to realize this system, a small System-on-a Chip (SoC) called Medical Domain Specific SOC, Type-I (MeSOC-I) has been developed. MeSOC-I enables an inner bladder pressure sensing system to conduct more than 72 hours measurement with a small battery.
Multi-Dimensional Parity Check (MDPC) code is an error correcting code which has been widely used... more Multi-Dimensional Parity Check (MDPC) code is an error correcting code which has been widely used for wireless communications under low error rate environment. In this study, a low-power processor for MDPC code processing is introduced and evaluated. Through experimental results, the proposed processor achieves about 90% lower in energy consumption compared with an implementation by a canonical RISC processor.
A low-energy ASIP with flexible exponential Golomb codec for lossless data compression toward artificial vision systems
2015 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2015
This paper proposes an application-domain specific instruction-set processor (ASIP) with dedicate... more This paper proposes an application-domain specific instruction-set processor (ASIP) with dedicated instructions for lossless data compression and decompression process to be used in artificial vision systems. Proposed ASIP has dedicated instructions to accelerate the performance to codec operations of Exponential Golomb coding, where the coding parameter value can be set by the user in order to maximize the compression ratio. Experimental results through simulation show that the proposed ASIP reduces execution cycles by 88% for compression and 42% for decompression, and reduces energy consumption by 85% for compression and 40% for decompression, compared with the base reduced instruction set computer processor.
A Block-Floating-Point Processor for Rapid Application Development
2007 IEEE International Conference on Acoustics, Speech and Signal Processing - ICASSP '07, 2007
This paper proposes an instruction set processor which uses hierarchical block-floating-point (H-... more This paper proposes an instruction set processor which uses hierarchical block-floating-point (H-BFP) arithmetic. H-BFP has been developed to provide efficient development approach for digital signal processing system. H-BFP offers highly abstracted computation model, and leads to cost-effective implementation. However, application development based on H-BFP is still time consuming task because of lacking high level programming language. In this paper, a processor architecture together with a set of instructions to support H-BFP are proposed. We also propose a related software development environment for efficient algorithm translation which generate high performance codes without any time consuming task. Experimental results show proposed environment achieves high performance signal processing systems with H-BFP processors.
In this paper, we propose a compiler generation method from architecture description language (AD... more In this paper, we propose a compiler generation method from architecture description language (ADL) of ASIP Integrated Development Environment. By using our proposed method the modification of compiler, due to changes in processor specification, becomes easier and the amount of description and design time can be reduced. In our experiments, we compared the description and design time of an ASIP using our proposed method and conventional method, which generates a compiler manually. The experimental results show that the proposed method can reduce both the amount of the description and the design time by approximately 80% as compared to conventional method.
Atsushi KISHIMOTO†, Nagisa ISHIURA††, Yuuki MASUI††, and Masaharu IMAI††† † Graduate School of Sc... more Atsushi KISHIMOTO†, Nagisa ISHIURA††, Yuuki MASUI††, and Masaharu IMAI††† † Graduate School of Science, Kwansei Gakuin University 2–1 Gakuen, Sanda, Hyogo, 669–1337, Japan †† Science and Technology, Kwansei Gakuin University 2–1 Gakuen, Sanda, Hyogo, 669–1337, Japan ††† Graduate School of Information Science and Technology, Osaka University 1–5 Yamadaoka, Suita, Osaka, 565–0871, Japan E-mail: †[email protected], ††{ishiura,bux65238}@ksc.kwansei.ac.jp, † † †[email protected]
This paper presents the methodology and the modeling constructs we have developed to capture the ... more This paper presents the methodology and the modeling constructs we have developed to capture the real time aspects of RTOS simulation models in a System Level Design Language (SLDL) like SystemC. We describe these constructs and show how they are used to build a simulation model of an RTOS kernel targeting the µ-ITRON OS specification standard.
This paper proposes a novel data compression method for artificial vision systems and its low-ene... more This paper proposes a novel data compression method for artificial vision systems and its low-energy implementation in order to reduce energy consumption in a wireless communication subsystem. The artificial vision systems are one of the methods for realizing visual prosthesis by controlling stimulus to visual nerves, and they consist of an inner stimulating unit and an outer image processing unit. The outer unit transmits information regarding stimulation to the inner unit via wireless communication, which occupies a large portion of the whole energy consumption. Reducing traffic in wireless communication is important to prevent damage caused by extra heat dissipation of the inner unit, which leads to excess energy consumption. The proposed compression method marks a higher compression ratio than the conventional compression methods by taking advantage of the analyses of stimuli position data, which is dominant in traffic. The proposed method is implemented as an application-domain specific instruction-set processor to achieve both configurability of stimulation control and compression efficiency. The evaluation results show that the proposed implementation reduces energy consumption by about 87% and 62% in the compression and decompression process, respectively. These results indicate that the proposed method can expect to reduce energy consumption in a wireless communication receiver dramatically.
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