In this paper, a comprehensive study of gate-induced drain leakage (GIDL) in conventional silicon... more In this paper, a comprehensive study of gate-induced drain leakage (GIDL) in conventional silicon-nanotube (Si-NT JLFET), SiGe Source/Drain silicon-nanotube junctionless field effect transistor (S/D Si-NT JLFET) and conventional nanowire (NW) have been performed using technology computer-aided design simulations. We have also demonstrated that inclusion of SiGe S/D in Si-NT JLFET reduced the OFF-state current by order of ~3 from NT JLFET and by order of ~6 from NW JLFET. The impact of variation of core gate thickness ([Formula: see text], germanium (Ge) content [Formula: see text], and location of SiGe in source and drain regions of the S/D Si-NT JLFET have been studied from the GIDL perspective. We found that SiGe S/D Si-NT JLFET exhibits impressively high [Formula: see text]/[Formula: see text] ratio [Formula: see text] with reduced lateral band-to-band tunneling (L-BTBT)-induced GIDL than the conventional nanowire device. The is due to SiGe S/D that creates a energy valence band discontinuity at source drain interfaces which limits the flow of electrons from channel to drain region in the OFF-state.
This paper presents three types of the microchannel which is used for the detection of cholera an... more This paper presents three types of the microchannel which is used for the detection of cholera and diarrhea. The three types of microchannels are namely cylindrical, rectangular, and triangular. The microchannels are designed and simulated using FEM tool. Capacitance, flow rate, flow velocity analysis are also carried out using FEM tool. The performance analysis of three channels are carried out using FEM tool. The principle used for the detection of cholera and diarrhea is a capacitive technique which have high sensitivity. The cylindrical channel has high performance than the rectangle and triangle based channel The time take by the cylindrical channel is the order of (6, 9 min) which is very less time for the detection than the rectangle (8, 13 min) and triangle (10, 15 min) based channels. The sensitivity and accuracy for the cylindrical channel is high than the rectangle and triangle based channels. Cylindrical channel have high performance than the rectangle and triangle based microchannels.
In this paper, a comprehensive study of gate-induced drain leakage (GIDL) in conventional silicon... more In this paper, a comprehensive study of gate-induced drain leakage (GIDL) in conventional silicon-nanotube (Si-NT JLFET), SiGe Source/Drain silicon-nanotube junctionless field effect transistor (S/D Si-NT JLFET) and conventional nanowire (NW) have been performed using technology computer-aided design simulations. We have also demonstrated that inclusion of SiGe S/D in Si-NT JLFET reduced the OFF-state current by order of ~3 from NT JLFET and by order of ~6 from NW JLFET. The impact of variation of core gate thickness ([Formula: see text], germanium (Ge) content [Formula: see text], and location of SiGe in source and drain regions of the S/D Si-NT JLFET have been studied from the GIDL perspective. We found that SiGe S/D Si-NT JLFET exhibits impressively high [Formula: see text]/[Formula: see text] ratio [Formula: see text] with reduced lateral band-to-band tunneling (L-BTBT)-induced GIDL than the conventional nanowire device. The is due to SiGe S/D that creates a energy valence band ...
REV Journal on Electronics and Communications, 2011
Thanks to the strong growth of MEMS technology, the Inertial Navigation System (INS) is widely ap... more Thanks to the strong growth of MEMS technology, the Inertial Navigation System (INS) is widely applied to navigation and guidance of moving objects. However, there exist errors in the inertial sensor’s signals that cause unacceptable drifts. To minimize these effects on the INS system, a GPS is usually employed simultaneously with an INS in order to increase the dimension of the system; the desired parameters are estimated by Kalman filtering technique applied to the enlarged system. In this paper, we present the design, simulation and performance analysis of an INS/GPS system using two parallel Kaman filters in order to increase the accuracy of the parameter estimation process. The results show that this system could be efficiently brought to practical applications.
In this paper, Partially Depleted Silicon on Insulator (PDSOI) MOSFET and Fully Depleted Silicon ... more In this paper, Partially Depleted Silicon on Insulator (PDSOI) MOSFET and Fully Depleted Silicon on Insulator (FDSOI) MOSFET are designed, and the impact of n-type doping concentration, work function variation, gate oxide, and silicon layer thickness on the performance of the device is studied and analyzed. The floating body and associated kink effects present in a PDSOI device are also investigated in detail. In addition to this, comparisons are made between PDSOI and FDSOI MOSFET to analyze their performance for various device parameters. The threshold voltage rises with increasing Si surface thickness and source doping, according to the data found. The drain current increases as the N-type doping concentration develops in both PD and FDSOI MOSFETs, and conduction begins after a concentration of 3x1017 cm−3 for PD and 2x1017 cm−3 for FDSOI, before which conduction is not effective. For the same n-type doping concentration and gate work function, FDSOI has a higher drain current than PDSOI. FDSOI is better than PDSOI since it eliminates PDSOI’s defects and enhances its performance. The Silvaco Atlas-2D TCAD simulator is used to simulate the device using conventional architecture and models.
In this paper, Partially Depleted Silicon on Insulator (PDSOI) MOSFET and Fully Depleted Silicon ... more In this paper, Partially Depleted Silicon on Insulator (PDSOI) MOSFET and Fully Depleted Silicon on Insulator (FDSOI) MOSFET are designed, and the impact of n-type doping concentration, work function variation, gate oxide, and silicon layer thickness on the performance of the device is studied and analyzed. The floating body and associated kink effects present in a PDSOI device are also investigated in detail. In addition to this, comparisons are made between PDSOI and FDSOI MOSFET to analyze their performance for various device parameters. The threshold voltage rises with increasing Si surface thickness and source doping, according to the data found. The drain current increases as the N-type doping concentration develops in both PD and FDSOI MOSFETs, and conduction begins after a concentration of 3x1017 cm−3 for PD and 2x1017 cm−3 for FDSOI, before which conduction is not effective. For the same n-type doping concentration and gate work function, FDSOI has a higher drain current th...
This paper presents a new design of charge plasma junctionless tunnel field effect transistor (CP... more This paper presents a new design of charge plasma junctionless tunnel field effect transistor (CP JLTFET) with improved ON current, surface potentials. For the ease of fabrication, source and drain regions are induced in intrinsic silicon material using proper metal workfunctions. The rate of tunneling of electrons is found more in case of proposed CP JLTFET. The cavity length is varied between 8 nm and 10 nm and different dielectric constants have been used. This increased the ON state performance of device i.e ON drive current, potential and electric field. The increase in tunneling of electrons is mainly due to high recombination of carriers in the channel region. The proposed device simulated their electrical parameters like drain current, surface potentials, electric field, and energy bands with different dielectric constants. These excellent performance parameters of the proposed device with an appropriate material can be used for sensing application of biomolecules by introducing a cavity in the device.
2020 IEEE Students Conference on Engineering & Systems (SCES)
In this work, Fully Depleted-Silicon on Insulator (FD-SOI) MOSFET is designed, and the impact of ... more In this work, Fully Depleted-Silicon on Insulator (FD-SOI) MOSFET is designed, and the impact of silicon thickness, source doping, and metal gate work function variations are investigated to analyze the various device performance parameters. Simulated results of ON current, OFF current, energy band diagram, gate capacitance, and drain capacitance are analyzed. In addition to this, drain induced barrier lowering (DIBL), the threshold voltage (Vth), sub-threshold slope (SS) variations are also evaluated. The results depict that the threshold voltage increases with the increment in Si surface thickness and source doping and it is 0.25V for 10 nm Si surface layer. The DIBL is 0.02 (V/V), and SS of 66.13 (mV/dec) is evaluated for the same Si surface layer thickness. Silvaco Atlas-2D TCAD simulator is used to estimate the various results.
In this paper, a linear graded double gate made of binary metal alloy PαQ1-α TFET (LDG-TFET) is p... more In this paper, a linear graded double gate made of binary metal alloy PαQ1-α TFET (LDG-TFET) is proposed and then it is used to implement distinct logic functions. To realize OR logic functions n-type LDG-TFET is used whereas to realize NAND logic functions implementations, a p-type LDG-TFET is used by individually biasing the two linearly graded gates against different combinations of input logics. The AND and NOR logic functions are implemented by overlapping the gate and source of the n-type and p-type of the proposed LDG-TFET device respectively. Introduced gate source overlapping in n-type and p-type LDG-TFET causes high barrier potential and thus reduces the current through it. To analyse the behaviour of each logic function, four combinations of inputs 00, 01, 10 and 11 are applied individually in to the two linearly graded gates and then the device’s energy band diagram and IV transfer characteristics are plotted and investigated. The highest energy band bending causes high on current indicates high logic level ‘1’ whereas lowest band bending and hence low Ion represents low logic level ‘0’. The input combination ‘00’ shows maximum tunneling for the NAND gate realization since in the both gate terminals low logic level is applied which is responsible for the large overlapping of the valance and the conduction band of the channel and the source. Also, a moderate tunneling has been seen for the logic level ‘01’ and ‘10’ these large and moderate tunneling correspond to output high logic level ‘1’ whereas no tunneling has been seen for the logic level ‘11’ which represents output low logic level ‘0’. This work enables area effective implementation of Boolean function.
This review describes an emerging field of electronics devices; electron spin exploitation use fo... more This review describes an emerging field of electronics devices; electron spin exploitation use for a further degree of freedom incorporation to charge state, with the significant feature like non-volatility, processing speed, reduction in power consumption, escalation in integration densities, data storage, and data transfer as compared to conventional CMOS devices. Moreover, this paper discussed challenges, limitations, and issues facing and CMOS technology and alternative solutions over CMOS. This article categorized all the details about the spin devices and strives to realize their prototype and functioning using the fundamental concept of quantum mechanics. The Magnetic RAM (MRAM) and spin-FET is a remarkable field of progress in the past few years over traditional CMOS, which urges advancement for conventional devices despite the significant challenges that lay ahead. Spin-FET's challenges are met by resolving issues in spin injection, spin transport, optical spin manipulation, and efforts in new materials fabrication. These devices contribute to the integrated circuit application of magnetic transistors towards reconfigurable logic-based devices with nonvolatility and reduction in power consumption.
In the present paper, design and performance assessment of hetero gate dielectric tunnel field ef... more In the present paper, design and performance assessment of hetero gate dielectric tunnel field effect transistor (TFET) with pocket doping at the source-channel interface is proposed for improving the switching characteristics of the device. This paper demonstrates an approach to suppress the ambipolarity and to improve the ION/IOFF ratio by investigating hetero gate dielectric TFET with Si0.5Ge0.5 pocket at channel side along with Ge as source. It enhances the dc device parameters such as threshold voltage, ION/IOFF ratio and subthreshold slope (SS) of the device as compared to the hetero gate Si0.5Ge0.5-channel TFET. To reduce the ambipolarity and to magnify ION of TFET, researchers have drawn their attention to incorporate some low bandgap material at the source-channel side. Therefore, SiGe, being group-IV elements are compatible with existing technology and introducing SiGe pocket with Ge as a source makes this device less prone to crystal defects like lattice mismatch. This paper reported a high ION/IOFF as 1015 and ION is 10 times higher in comparison to SiGe channel TFET. The impact of the variation of the doping concentration on different regimes of operations of the device characteristics has also been investigated. Further, the incorporation of the linear modulation of gate metal work function from the source end to drain end leads further enhancement in the device performance as it improves the ION while keeping the IOFF same over the single gate metal work function and it also achieves SS of 16.6 mV/decade. Comparative analysis of simulated results of RF/analog performance parameters of the LM-Si0.5Ge0.5-pocket TFET and LM-Si0.5Ge0.5-channel TFET has also been done. Our study validates the LM-Si0.5Ge0.5-pocket TFET device suitability for analog application as it achieves higher transconductance, cut-off frequency, gain bandwidth product (GBP), transgeneration factor (TGF) and transconductance frequency product (TFP) etc.
Transactions on Electrical and Electronic Materials, 2021
This submitted work presents the 2-dimensional analytical modeling of Tunnel FET’s in considerati... more This submitted work presents the 2-dimensional analytical modeling of Tunnel FET’s in consideration with the inherent properties of dual modulation effect. This effect explains the concept of regulating both gate and also the drain terminal biasing voltage on device surface potential and hence on the tunneling drain current model, which uses the device surface potential modeling as basis of deriving the TFET current model. The model is developed using basic 2-D Poisson’s equation. This analytical model embraces both the biasing voltage effect at gate and drain terminal respectively. The results procured from the submitted work are in perfect agreement with TCAD simulations results and depletion width of various regions defined in TFET is accurate and can also be explained theoretically.
In this paper, a novel n + SiGe pocket layer gate stacked VTFET doping less charge plasma is prop... more In this paper, a novel n + SiGe pocket layer gate stacked VTFET doping less charge plasma is proposed and analyzed using Silvaco TCAD simulation software. The proposed device will be worked as a transducer sensor which is based upon the principle of the electrostatic charge plasma. The inclusion of doping less charge plasma will ease the device in terms of cost production and form random dopant fluctuation (RDF). The inclusion of charge plasma with gate stacking will enhance the electrostatics control over the gate in order to gain the variation of drain current to boost the current sensitivity. The selection width of the High-K dielectric constant material with SiO2 will filter out using equivalent gate oxide thickness. The physics behind the change is work function of the gate material in the presence of the gas material is the dissociation and absorption of gas molecule via diffusion process to the catalytic gate metal of the device. In addition, n + SiGe pocket layer is introducing to suppress the tunneling barrier at source channel interface due to reduction in the band gap energy material from 1.1 to 0.7 eV. This paper analysis with oxygen and ammonia gases forms different introduced gate metal electrode such as Silver (m1 = 4.26–4.46 eV), Molybdenum (m2 = 4.40–4.60 eV), Ruthenium (m3 = 4.71–4.91 eV), and Cobalt (m4 = 5.0–5.20 eV). In this regard, the current sensitivity, electric filed, surface potential, energy band gap and other electrical characteristics with different drain and gate bias with suitable range is operated. The vertical distribution of the channel concentration will improve the device scalability. To test changes in device sensitivity of the catalytic material of the gate electrode will increases as a work function with the range of 50, 100, 150, 200, and 250 meV. The reported sensitivity (Idon/Idoff) is higher for lower work function i.e. for Silver, Cobalt, Molybdenum and Ruthenium the sensitivity is 4.18 × 102, 3.49 × 102, 1.02 × 103 and 2.79 × 101 respectively.
Proceedings of International Conference on Women Researchers in Electronics and Computing, 2021
In this investigated work, we have analysed the miscellaneous figure of merit for Double metal Tr... more In this investigated work, we have analysed the miscellaneous figure of merit for Double metal Triple gate TFET. Various techniques have been utilized to improve the ON-state driven current in the drain by doing a comprehensive analysis. Different techniques are examined and correlated by using the TCAD Silvaco tool to get excellent ON current. Further work function engineering has been done in the optimized DMTG-TFET to increase its performance and finally, we introduce pocket doping that increases the ON current (2.34×10-3) and also ION/IOFF ratio (4.36×1014) with subthreshold (SS) of 25.8mV/decade. The pocket doped DMTG-TFET adequately suppress the ambipolarity and endeavour about 20 times higher ION as compared to conventional DMTG-TFET.
In this paper, a comprehensive study of gate-induced drain leakage (GIDL) in conventional silicon... more In this paper, a comprehensive study of gate-induced drain leakage (GIDL) in conventional silicon-nanotube (Si-NT JLFET), SiGe Source/Drain silicon-nanotube junctionless field effect transistor (S/D Si-NT JLFET) and conventional nanowire (NW) have been performed using technology computer-aided design simulations. We have also demonstrated that inclusion of SiGe S/D in Si-NT JLFET reduced the OFF-state current by order of ~3 from NT JLFET and by order of ~6 from NW JLFET. The impact of variation of core gate thickness ([Formula: see text], germanium (Ge) content [Formula: see text], and location of SiGe in source and drain regions of the S/D Si-NT JLFET have been studied from the GIDL perspective. We found that SiGe S/D Si-NT JLFET exhibits impressively high [Formula: see text]/[Formula: see text] ratio [Formula: see text] with reduced lateral band-to-band tunneling (L-BTBT)-induced GIDL than the conventional nanowire device. The is due to SiGe S/D that creates a energy valence band discontinuity at source drain interfaces which limits the flow of electrons from channel to drain region in the OFF-state.
This paper presents three types of the microchannel which is used for the detection of cholera an... more This paper presents three types of the microchannel which is used for the detection of cholera and diarrhea. The three types of microchannels are namely cylindrical, rectangular, and triangular. The microchannels are designed and simulated using FEM tool. Capacitance, flow rate, flow velocity analysis are also carried out using FEM tool. The performance analysis of three channels are carried out using FEM tool. The principle used for the detection of cholera and diarrhea is a capacitive technique which have high sensitivity. The cylindrical channel has high performance than the rectangle and triangle based channel The time take by the cylindrical channel is the order of (6, 9 min) which is very less time for the detection than the rectangle (8, 13 min) and triangle (10, 15 min) based channels. The sensitivity and accuracy for the cylindrical channel is high than the rectangle and triangle based channels. Cylindrical channel have high performance than the rectangle and triangle based microchannels.
In this paper, a comprehensive study of gate-induced drain leakage (GIDL) in conventional silicon... more In this paper, a comprehensive study of gate-induced drain leakage (GIDL) in conventional silicon-nanotube (Si-NT JLFET), SiGe Source/Drain silicon-nanotube junctionless field effect transistor (S/D Si-NT JLFET) and conventional nanowire (NW) have been performed using technology computer-aided design simulations. We have also demonstrated that inclusion of SiGe S/D in Si-NT JLFET reduced the OFF-state current by order of ~3 from NT JLFET and by order of ~6 from NW JLFET. The impact of variation of core gate thickness ([Formula: see text], germanium (Ge) content [Formula: see text], and location of SiGe in source and drain regions of the S/D Si-NT JLFET have been studied from the GIDL perspective. We found that SiGe S/D Si-NT JLFET exhibits impressively high [Formula: see text]/[Formula: see text] ratio [Formula: see text] with reduced lateral band-to-band tunneling (L-BTBT)-induced GIDL than the conventional nanowire device. The is due to SiGe S/D that creates a energy valence band ...
REV Journal on Electronics and Communications, 2011
Thanks to the strong growth of MEMS technology, the Inertial Navigation System (INS) is widely ap... more Thanks to the strong growth of MEMS technology, the Inertial Navigation System (INS) is widely applied to navigation and guidance of moving objects. However, there exist errors in the inertial sensor’s signals that cause unacceptable drifts. To minimize these effects on the INS system, a GPS is usually employed simultaneously with an INS in order to increase the dimension of the system; the desired parameters are estimated by Kalman filtering technique applied to the enlarged system. In this paper, we present the design, simulation and performance analysis of an INS/GPS system using two parallel Kaman filters in order to increase the accuracy of the parameter estimation process. The results show that this system could be efficiently brought to practical applications.
In this paper, Partially Depleted Silicon on Insulator (PDSOI) MOSFET and Fully Depleted Silicon ... more In this paper, Partially Depleted Silicon on Insulator (PDSOI) MOSFET and Fully Depleted Silicon on Insulator (FDSOI) MOSFET are designed, and the impact of n-type doping concentration, work function variation, gate oxide, and silicon layer thickness on the performance of the device is studied and analyzed. The floating body and associated kink effects present in a PDSOI device are also investigated in detail. In addition to this, comparisons are made between PDSOI and FDSOI MOSFET to analyze their performance for various device parameters. The threshold voltage rises with increasing Si surface thickness and source doping, according to the data found. The drain current increases as the N-type doping concentration develops in both PD and FDSOI MOSFETs, and conduction begins after a concentration of 3x1017 cm−3 for PD and 2x1017 cm−3 for FDSOI, before which conduction is not effective. For the same n-type doping concentration and gate work function, FDSOI has a higher drain current than PDSOI. FDSOI is better than PDSOI since it eliminates PDSOI’s defects and enhances its performance. The Silvaco Atlas-2D TCAD simulator is used to simulate the device using conventional architecture and models.
In this paper, Partially Depleted Silicon on Insulator (PDSOI) MOSFET and Fully Depleted Silicon ... more In this paper, Partially Depleted Silicon on Insulator (PDSOI) MOSFET and Fully Depleted Silicon on Insulator (FDSOI) MOSFET are designed, and the impact of n-type doping concentration, work function variation, gate oxide, and silicon layer thickness on the performance of the device is studied and analyzed. The floating body and associated kink effects present in a PDSOI device are also investigated in detail. In addition to this, comparisons are made between PDSOI and FDSOI MOSFET to analyze their performance for various device parameters. The threshold voltage rises with increasing Si surface thickness and source doping, according to the data found. The drain current increases as the N-type doping concentration develops in both PD and FDSOI MOSFETs, and conduction begins after a concentration of 3x1017 cm−3 for PD and 2x1017 cm−3 for FDSOI, before which conduction is not effective. For the same n-type doping concentration and gate work function, FDSOI has a higher drain current th...
This paper presents a new design of charge plasma junctionless tunnel field effect transistor (CP... more This paper presents a new design of charge plasma junctionless tunnel field effect transistor (CP JLTFET) with improved ON current, surface potentials. For the ease of fabrication, source and drain regions are induced in intrinsic silicon material using proper metal workfunctions. The rate of tunneling of electrons is found more in case of proposed CP JLTFET. The cavity length is varied between 8 nm and 10 nm and different dielectric constants have been used. This increased the ON state performance of device i.e ON drive current, potential and electric field. The increase in tunneling of electrons is mainly due to high recombination of carriers in the channel region. The proposed device simulated their electrical parameters like drain current, surface potentials, electric field, and energy bands with different dielectric constants. These excellent performance parameters of the proposed device with an appropriate material can be used for sensing application of biomolecules by introducing a cavity in the device.
2020 IEEE Students Conference on Engineering & Systems (SCES)
In this work, Fully Depleted-Silicon on Insulator (FD-SOI) MOSFET is designed, and the impact of ... more In this work, Fully Depleted-Silicon on Insulator (FD-SOI) MOSFET is designed, and the impact of silicon thickness, source doping, and metal gate work function variations are investigated to analyze the various device performance parameters. Simulated results of ON current, OFF current, energy band diagram, gate capacitance, and drain capacitance are analyzed. In addition to this, drain induced barrier lowering (DIBL), the threshold voltage (Vth), sub-threshold slope (SS) variations are also evaluated. The results depict that the threshold voltage increases with the increment in Si surface thickness and source doping and it is 0.25V for 10 nm Si surface layer. The DIBL is 0.02 (V/V), and SS of 66.13 (mV/dec) is evaluated for the same Si surface layer thickness. Silvaco Atlas-2D TCAD simulator is used to estimate the various results.
In this paper, a linear graded double gate made of binary metal alloy PαQ1-α TFET (LDG-TFET) is p... more In this paper, a linear graded double gate made of binary metal alloy PαQ1-α TFET (LDG-TFET) is proposed and then it is used to implement distinct logic functions. To realize OR logic functions n-type LDG-TFET is used whereas to realize NAND logic functions implementations, a p-type LDG-TFET is used by individually biasing the two linearly graded gates against different combinations of input logics. The AND and NOR logic functions are implemented by overlapping the gate and source of the n-type and p-type of the proposed LDG-TFET device respectively. Introduced gate source overlapping in n-type and p-type LDG-TFET causes high barrier potential and thus reduces the current through it. To analyse the behaviour of each logic function, four combinations of inputs 00, 01, 10 and 11 are applied individually in to the two linearly graded gates and then the device’s energy band diagram and IV transfer characteristics are plotted and investigated. The highest energy band bending causes high on current indicates high logic level ‘1’ whereas lowest band bending and hence low Ion represents low logic level ‘0’. The input combination ‘00’ shows maximum tunneling for the NAND gate realization since in the both gate terminals low logic level is applied which is responsible for the large overlapping of the valance and the conduction band of the channel and the source. Also, a moderate tunneling has been seen for the logic level ‘01’ and ‘10’ these large and moderate tunneling correspond to output high logic level ‘1’ whereas no tunneling has been seen for the logic level ‘11’ which represents output low logic level ‘0’. This work enables area effective implementation of Boolean function.
This review describes an emerging field of electronics devices; electron spin exploitation use fo... more This review describes an emerging field of electronics devices; electron spin exploitation use for a further degree of freedom incorporation to charge state, with the significant feature like non-volatility, processing speed, reduction in power consumption, escalation in integration densities, data storage, and data transfer as compared to conventional CMOS devices. Moreover, this paper discussed challenges, limitations, and issues facing and CMOS technology and alternative solutions over CMOS. This article categorized all the details about the spin devices and strives to realize their prototype and functioning using the fundamental concept of quantum mechanics. The Magnetic RAM (MRAM) and spin-FET is a remarkable field of progress in the past few years over traditional CMOS, which urges advancement for conventional devices despite the significant challenges that lay ahead. Spin-FET's challenges are met by resolving issues in spin injection, spin transport, optical spin manipulation, and efforts in new materials fabrication. These devices contribute to the integrated circuit application of magnetic transistors towards reconfigurable logic-based devices with nonvolatility and reduction in power consumption.
In the present paper, design and performance assessment of hetero gate dielectric tunnel field ef... more In the present paper, design and performance assessment of hetero gate dielectric tunnel field effect transistor (TFET) with pocket doping at the source-channel interface is proposed for improving the switching characteristics of the device. This paper demonstrates an approach to suppress the ambipolarity and to improve the ION/IOFF ratio by investigating hetero gate dielectric TFET with Si0.5Ge0.5 pocket at channel side along with Ge as source. It enhances the dc device parameters such as threshold voltage, ION/IOFF ratio and subthreshold slope (SS) of the device as compared to the hetero gate Si0.5Ge0.5-channel TFET. To reduce the ambipolarity and to magnify ION of TFET, researchers have drawn their attention to incorporate some low bandgap material at the source-channel side. Therefore, SiGe, being group-IV elements are compatible with existing technology and introducing SiGe pocket with Ge as a source makes this device less prone to crystal defects like lattice mismatch. This paper reported a high ION/IOFF as 1015 and ION is 10 times higher in comparison to SiGe channel TFET. The impact of the variation of the doping concentration on different regimes of operations of the device characteristics has also been investigated. Further, the incorporation of the linear modulation of gate metal work function from the source end to drain end leads further enhancement in the device performance as it improves the ION while keeping the IOFF same over the single gate metal work function and it also achieves SS of 16.6 mV/decade. Comparative analysis of simulated results of RF/analog performance parameters of the LM-Si0.5Ge0.5-pocket TFET and LM-Si0.5Ge0.5-channel TFET has also been done. Our study validates the LM-Si0.5Ge0.5-pocket TFET device suitability for analog application as it achieves higher transconductance, cut-off frequency, gain bandwidth product (GBP), transgeneration factor (TGF) and transconductance frequency product (TFP) etc.
Transactions on Electrical and Electronic Materials, 2021
This submitted work presents the 2-dimensional analytical modeling of Tunnel FET’s in considerati... more This submitted work presents the 2-dimensional analytical modeling of Tunnel FET’s in consideration with the inherent properties of dual modulation effect. This effect explains the concept of regulating both gate and also the drain terminal biasing voltage on device surface potential and hence on the tunneling drain current model, which uses the device surface potential modeling as basis of deriving the TFET current model. The model is developed using basic 2-D Poisson’s equation. This analytical model embraces both the biasing voltage effect at gate and drain terminal respectively. The results procured from the submitted work are in perfect agreement with TCAD simulations results and depletion width of various regions defined in TFET is accurate and can also be explained theoretically.
In this paper, a novel n + SiGe pocket layer gate stacked VTFET doping less charge plasma is prop... more In this paper, a novel n + SiGe pocket layer gate stacked VTFET doping less charge plasma is proposed and analyzed using Silvaco TCAD simulation software. The proposed device will be worked as a transducer sensor which is based upon the principle of the electrostatic charge plasma. The inclusion of doping less charge plasma will ease the device in terms of cost production and form random dopant fluctuation (RDF). The inclusion of charge plasma with gate stacking will enhance the electrostatics control over the gate in order to gain the variation of drain current to boost the current sensitivity. The selection width of the High-K dielectric constant material with SiO2 will filter out using equivalent gate oxide thickness. The physics behind the change is work function of the gate material in the presence of the gas material is the dissociation and absorption of gas molecule via diffusion process to the catalytic gate metal of the device. In addition, n + SiGe pocket layer is introducing to suppress the tunneling barrier at source channel interface due to reduction in the band gap energy material from 1.1 to 0.7 eV. This paper analysis with oxygen and ammonia gases forms different introduced gate metal electrode such as Silver (m1 = 4.26–4.46 eV), Molybdenum (m2 = 4.40–4.60 eV), Ruthenium (m3 = 4.71–4.91 eV), and Cobalt (m4 = 5.0–5.20 eV). In this regard, the current sensitivity, electric filed, surface potential, energy band gap and other electrical characteristics with different drain and gate bias with suitable range is operated. The vertical distribution of the channel concentration will improve the device scalability. To test changes in device sensitivity of the catalytic material of the gate electrode will increases as a work function with the range of 50, 100, 150, 200, and 250 meV. The reported sensitivity (Idon/Idoff) is higher for lower work function i.e. for Silver, Cobalt, Molybdenum and Ruthenium the sensitivity is 4.18 × 102, 3.49 × 102, 1.02 × 103 and 2.79 × 101 respectively.
Proceedings of International Conference on Women Researchers in Electronics and Computing, 2021
In this investigated work, we have analysed the miscellaneous figure of merit for Double metal Tr... more In this investigated work, we have analysed the miscellaneous figure of merit for Double metal Triple gate TFET. Various techniques have been utilized to improve the ON-state driven current in the drain by doing a comprehensive analysis. Different techniques are examined and correlated by using the TCAD Silvaco tool to get excellent ON current. Further work function engineering has been done in the optimized DMTG-TFET to increase its performance and finally, we introduce pocket doping that increases the ON current (2.34×10-3) and also ION/IOFF ratio (4.36×1014) with subthreshold (SS) of 25.8mV/decade. The pocket doped DMTG-TFET adequately suppress the ambipolarity and endeavour about 20 times higher ION as compared to conventional DMTG-TFET.
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Papers by Girish Wadhwa