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G. Ghibaudo

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Giuseppe Iannaccone

Università di Pisa

Aix-Marseille University

NJIT

Riccardo Gusmeroli

Universidade Unisantos

Bal Chand Nagar

Rakesh Velugula

Christophe Lallement

Damien Deleruyelle

Aix-Marseille Université

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Papers by G. Ghibaudo

Experimental and theoretical analysis of scaling issues in dual-bit discrete trap non-volatile memories

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 2005

Here we present an experimental and theoretical analysis of dual-bit DT-NVMs. In particular data ... more Here we present an experimental and theoretical analysis of dual-bit DT-NVMs. In particular data retention experiments on bulk and SOI silicon nanocrystal memory devices (Fig. 1) and their interpretation through a surface potential based model are shown (4). Our model is then exploited to investigate the main issues posed by dual-bit reading, when the dimensions of bulk and SOI devices are scaled down. We present two different reading schemes for a scaled device and we show that dual-bit performance of DT-NVMs, charged on both sides, is preserved even when the two pockets of charge coalesce. Finally, we conclude that both bulk and SOI dualbit architectures are promising for memory cells with gate lengths down to 30-50 nm.

Oxide thickness extraction methods in the nanometer range for statistical measurements

Solid-State Electronics, 2002

Simple techniques are proposed to extract the oxide thickness from C(V) characteristics in the na... more Simple techniques are proposed to extract the oxide thickness from C(V) characteristics in the nanometer range. A first comparative method using no fitting parameter allows the oxide thickness extraction by comparison to a reference sample on the same technology. In a second method, the oxide thickness is directly extracted assuming one parameter (associated to the carrier statistics). Both techniques are experimentally and theoretically justified. They open new perspectives to statistical oxide thickness measurements.

Comparison of two analog buffers implemented with low-temperature polysilicon thin-film transistors for active matrix displays applications

physica status solidi (c), 2008

1 Electronics Lab., Department of Physics, Aristotle University of Thessaloniki, 54124 Thessaloni... more

NANOSIL network of excellence—silicon-based nanostructures and nanodevices for long-term nanoelectronics applications

Materials Science in Semiconductor Processing, 2008

NANOSIL Network of Excellence [NANOSIL NoE web site〈 www. nanosil-noe. eu〉], funded by the Europe... more NANOSIL Network of Excellence [NANOSIL NoE web site〈 www. nanosil-noe. eu〉], funded by the European Commission in the 7th Framework Programme (ICT-FP7, no 216171), aims at European scale integration of the excellent European research laboratories and their capabilities in order to strengthen scientific and technological excellence in the field of nanoelectronic materials and devices for terascale integrated circuits (ICs), and to disseminating the results in a wide scientific and industrial community. NANOSIL is ...

Low-frequency noise characterization of n- and p-MOSFET's with ultrathin oxynitride gate films

IEEE Electron Device Letters, 1996

Abstruct-MOSFET's with ultrathin (5 to 8.5 nm) silicon oxynitride gate film prepared by low-press... more Abstruct-MOSFET's with ultrathin (5 to 8.5 nm) silicon oxynitride gate film prepared by low-pressure rapid thermal chemical vapor deposition (RTCVD) using SiH4, NzO and NH3 gases, are studied by low-frequency noise measurements (1 Hz up to 5 kHz). The analysis takes into account the correlated mobility fluctuations induced by those of the interfacial oxide charge. The nitrogen concentration, determined from SIMS analysis, varies from 0 to 11% atomic percentage. A comparison of the electrical properties between thermal and silicon oxynitride films is presented. The increasing LF noise signal with nitrogen atomic percentage indicates the presence of a higher density of slow interface traps with increasing nitrogen incorporation. Besides, a higher Coulomb scattering rate due to the nitridation induced interface charge explains reasonably well the degradation of the low field mobility after nitridation.

How small the contacts could be optimal for nanoscale organic transistors?

Organic Electronics, 2013

ABSTRACT We report on a study seeking an optimized contact configuration for organic transistors ... more ABSTRACT We report on a study seeking an optimized contact configuration for organic transistors that minimizes contact effects but maintains smallest contact size. We begin with the bulk access resistance in staggered transistors which results from the charge transport through the organic semiconductor film. Bulk access resistance is an intrinsic contributor to the contact resistance which has been little understood due to lack of a reliable study tool. In this work, we utilize the inner transported power inside the semiconductor film as a medium to investigate the contact resistance and the relevant contact effects. We examine the influences of the organic film thickness (tSC), the channel length (L), the underlying charge transport and various organic semiconductor materials with variable carrier mobility. A roughly optimal contact length (LC) of LC0 ≈ 6tSC is obtained. The results reveal that besides the device architecture the underlying charge transport should be also taken into account in designing organic transistors for practical application.

In-situ comparison of Si/High-K and Si/SiO2 interface properties in FD SOI MOSFETs operated at low temperature

Extended Abstracts of the 2007 International Conference on Solid State Devices and Materials, 2007

Detailed measurements of front and back channel characteristics in advanced SOI MOSFETs are used ... more Detailed measurements of front and back channel characteristics in advanced SOI MOSFETs are used to reveal the transport properties at the corresponding Si/High-K and Si/SiO 2 interfaces. Low-temperature operation magnifies the difference between these two interfaces in terms of carrier mobility. The mobility is lower at the Si/High-K interface and increases less rapidly at low temperature, reflecting more complex scattering mechanisms. We also discuss the short-channel effects and the difference between N and P channels.

Impact of a HTO/Al2O3 bi-layer blocking oxide in nitride-trap non-volatile memories

Solid-State Electronics, 2009

In this work, we present an experimental and theoretical study of nitride trap devices with a HTO... more In this work, we present an experimental and theoretical study of nitride trap devices with a HTO/Al2O3 bi-layer blocking oxide. Such SAONOS (Silicon/Alumina/ HTO/Nitride/Oxide/Silicon) devices are compared with standard SONOS (Silicon/HTO/Nitride/Oxide/Silicon) and SANOS (Silicon/Alumina/Nitride/Oxide/Silicon) memories. The role of the different layers (blocking oxide and control gate) is deeply analyzed, focusing on their impact on memory performance and reliability. Then, a semi-analytical model is developed, which provides a good understanding of the physical mechanisms at the origin of program/erase characteristics.

Electrostatic effect of localised charge in dual bit memory cells with discrete traps

The following article, presented at ESSDERC 2004 conference, illustrates the capability of ATLAS ... more

Drift-diffusion and Ballistic Mobility Characterization in Nano CMOS Devices

National audienc

Unexpected impact of germanium content in SiGe bulk PMOSFETs

Solid-State Electronics, 2013

ABSTRACT In this paper, we investigate the impact of silicon–germanium channel on PMOSFETs with T... more ABSTRACT In this paper, we investigate the impact of silicon–germanium channel on PMOSFETs with TiN metal and HfSiON dielectrics gate stack. Performance increase with Ge incorporation in the channel is higher than theoretically expected. Threshold voltage is outstandingly lowered and mobility is highly improved. Poisson–Schrödinger simulations are carried out to interpret the experimental results. Room as well as low temperature mobility measurements and low frequency noise analysis are performed in order to better understand this unforeseen germanium influence. Smaller Coulomb scattering rates are clearly evidenced in SiGe devices, probably explaining the higher mobility.

Low Frequency Noise Performance in TiN/HfO2 Fully Depleted SOI nMOSFET

2006 IEEE international SOI Conferencee Proceedings, 2006

The low frequency noise of TiN/HfO2 fully-depleted SOI nMOSFET is studied for different front and... more

Study of an embedded buried SiGe structure as a mobility booster for fully-depleted SOI MOSFETs at the 10nm node

Solid-State Electronics, 2014

This paper presents mechanical simulations results of an innovative strain transfer structure con... more This paper presents mechanical simulations results of an innovative strain transfer structure consisting in a buried compressive SiGe layer embedded under an ultra-thin buried oxide (BOX). We studied the influence of different dimensions including the active area and determined optimal parameters of the SiGe layer maximizing the strain. We demonstrate a transfer of a tensile stress up to 1.3 GPa in the silicon. Thanks to 3D simulations and the study of stress profiles in the SOI, the electron mobility enhancement is estimated to be about 80% for logic transistors at the 10 nm node. The strain induced in the channel by the edge relaxation of an embedded buried SiGe layer is compared to strained Silicon-On-Insulator (sSOI) wafers and strained nitride layer for Fully Depleted Silicon-On-Insulator (FDSOI).

Revisited approach for the characterization of Gate Induced Drain Leakage

Solid-State Electronics, 2012

ABSTRACT This work presents a critical review and a re-investigation of the electrical characteri... more ABSTRACT This work presents a critical review and a re-investigation of the electrical characterization of Gate Induced Drain Leakage (GIDL) and . The underlying assumptions of the previously proposed extraction methods are exposed and their ability to capture Band-to-Trap mechanisms is discussed. A new approach is introduced to overcome some of the limiting assumptions made by the previous extraction methods. This new approach is benchmarked against the previously proposed ones. The results show that it enables a better extraction of the GIDL parameters compared to the conventional methods, by using the voltage dependency of the activation energy to gain insight in the electric field responsible for Band-to-Band Tunneling in the device. Finally, the experimental application of this new approach is carried out on cold process FDSOI MOSFET and confirms the ability of this new method to quantify the impact of trap assisted tunneling on GIDL.

Comparative study of circuit perspectives for multi-gate structures at sub-10nm node

Solid-State Electronics, 2012

This work presents a comparative study between planar and vertical (FinFETs) multi-gate structure... more This work presents a comparative study between planar and vertical (FinFETs) multi-gate structures for 2017 ITRS specifications circuit perspectives. Propagation delays are simulated for inverter chain and NAND gate chain. Finally, the impact of the width is investigated on several design rules for FinFETs configurations.

Bardeen's approach for tunneling evaluation in MOS structures

Solid-State Electronics, 2002

This work is a presentation of the so-called “Bardeen's approach” formalism for tunneling. T... more This work is a presentation of the so-called “Bardeen's approach” formalism for tunneling. The way to use it for the modeling of tunnel current in MOS structure is also discussed. The theoretical background of this formalism is presented in an understandable way, and compared with other approaches. Then, an original method to use it is also proposed, which allows both numerical and analytical calculations.

Carrier mobility in advanced CMOS devices with metal gate and HfO2 gate dielectric

Solid-State Electronics, 2003

ABSTRACT Advanced channel N and P MOSFETs with HfO2 gate dielectric and metal gate have been fabr... more ABSTRACT Advanced channel N and P MOSFETs with HfO2 gate dielectric and metal gate have been fabricated and exhibit high performance. The effective mobility has been characterized at various temperatures for NMOS and PMOS devices. The electron mobility is lower than in SiO2, whereas the hole mobility is relatively unaffected at room temperature but also degraded at low temperatures. The mobility degradation after constant voltage stress suggests a more important Coulomb scattering contribution to mobility as compared to SiO2.

Study of stress induced leakage current by using high resolution measurements

Microelectronics Reliability, 1999

A thorough characterization of stress-induced leakage currents (SILCs) for a 10nm-thick oxide, by... more A thorough characterization of stress-induced leakage currents (SILCs) for a 10nm-thick oxide, by using the floating-gate technique, is presented. The obtained current is modeled by a volume-limited conduction mechanism. Experimental and model suggest that SILC conduction mechanism is the same in thin as well as in thick oxides.

Wear-out, breakdown occurrence and failure detection in 18–25 Å ultrathin oxides

Microelectronics Reliability, 2001

In this paper, a comprehensive description of the ultrathin oxide failure evolution is presented.... more In this paper, a comprehensive description of the ultrathin oxide failure evolution is presented. For sub-25 Å, Hard BD is no longer hard. A complete description of the novel failure manifestation (progressive breakdown) is done. Associated wear-out is modelled and a physical mechanism is proposed. Finally, the relevance of the failure definition is discussed. It is a crucial point, to

Charge trapping in SiO2/HfO2/TiN gate stack

Microelectronics Reliability, 2003

ABSTRACT Further scaling of CMOS technologies will require the use of high K gate dielectrics in ... more ABSTRACT Further scaling of CMOS technologies will require the use of high K gate dielectrics in order to keep a sufficiently low leakage current. The electrical properties of these new materials, especially in terms of interface quality, mobility and reliability can be regarded as a major concern. In this work, we have studied charge trapping in HfO2/SiO2 gate dielectric stacks using CVS and CCS with gate and drain currents vs gate voltage measurements. We found positive charge trapping for gate injection and negative charge trapping for substrate injection. We also gained more insight into the influence on charge trapping of the buffer SiO2 layer.

Experimental and theoretical analysis of scaling issues in dual-bit discrete trap non-volatile memories

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 2005

Here we present an experimental and theoretical analysis of dual-bit DT-NVMs. In particular data ... more Here we present an experimental and theoretical analysis of dual-bit DT-NVMs. In particular data retention experiments on bulk and SOI silicon nanocrystal memory devices (Fig. 1) and their interpretation through a surface potential based model are shown (4). Our model is then exploited to investigate the main issues posed by dual-bit reading, when the dimensions of bulk and SOI devices are scaled down. We present two different reading schemes for a scaled device and we show that dual-bit performance of DT-NVMs, charged on both sides, is preserved even when the two pockets of charge coalesce. Finally, we conclude that both bulk and SOI dualbit architectures are promising for memory cells with gate lengths down to 30-50 nm.

Oxide thickness extraction methods in the nanometer range for statistical measurements

Solid-State Electronics, 2002

Simple techniques are proposed to extract the oxide thickness from C(V) characteristics in the na... more Simple techniques are proposed to extract the oxide thickness from C(V) characteristics in the nanometer range. A first comparative method using no fitting parameter allows the oxide thickness extraction by comparison to a reference sample on the same technology. In a second method, the oxide thickness is directly extracted assuming one parameter (associated to the carrier statistics). Both techniques are experimentally and theoretically justified. They open new perspectives to statistical oxide thickness measurements.

Comparison of two analog buffers implemented with low-temperature polysilicon thin-film transistors for active matrix displays applications

physica status solidi (c), 2008

1 Electronics Lab., Department of Physics, Aristotle University of Thessaloniki, 54124 Thessaloni... more

NANOSIL network of excellence—silicon-based nanostructures and nanodevices for long-term nanoelectronics applications

Materials Science in Semiconductor Processing, 2008

NANOSIL Network of Excellence [NANOSIL NoE web site〈 www. nanosil-noe. eu〉], funded by the Europe... more NANOSIL Network of Excellence [NANOSIL NoE web site〈 www. nanosil-noe. eu〉], funded by the European Commission in the 7th Framework Programme (ICT-FP7, no 216171), aims at European scale integration of the excellent European research laboratories and their capabilities in order to strengthen scientific and technological excellence in the field of nanoelectronic materials and devices for terascale integrated circuits (ICs), and to disseminating the results in a wide scientific and industrial community. NANOSIL is ...

Low-frequency noise characterization of n- and p-MOSFET's with ultrathin oxynitride gate films

IEEE Electron Device Letters, 1996

Abstruct-MOSFET's with ultrathin (5 to 8.5 nm) silicon oxynitride gate film prepared by low-press... more Abstruct-MOSFET's with ultrathin (5 to 8.5 nm) silicon oxynitride gate film prepared by low-pressure rapid thermal chemical vapor deposition (RTCVD) using SiH4, NzO and NH3 gases, are studied by low-frequency noise measurements (1 Hz up to 5 kHz). The analysis takes into account the correlated mobility fluctuations induced by those of the interfacial oxide charge. The nitrogen concentration, determined from SIMS analysis, varies from 0 to 11% atomic percentage. A comparison of the electrical properties between thermal and silicon oxynitride films is presented. The increasing LF noise signal with nitrogen atomic percentage indicates the presence of a higher density of slow interface traps with increasing nitrogen incorporation. Besides, a higher Coulomb scattering rate due to the nitridation induced interface charge explains reasonably well the degradation of the low field mobility after nitridation.

How small the contacts could be optimal for nanoscale organic transistors?

Organic Electronics, 2013

ABSTRACT We report on a study seeking an optimized contact configuration for organic transistors ... more ABSTRACT We report on a study seeking an optimized contact configuration for organic transistors that minimizes contact effects but maintains smallest contact size. We begin with the bulk access resistance in staggered transistors which results from the charge transport through the organic semiconductor film. Bulk access resistance is an intrinsic contributor to the contact resistance which has been little understood due to lack of a reliable study tool. In this work, we utilize the inner transported power inside the semiconductor film as a medium to investigate the contact resistance and the relevant contact effects. We examine the influences of the organic film thickness (tSC), the channel length (L), the underlying charge transport and various organic semiconductor materials with variable carrier mobility. A roughly optimal contact length (LC) of LC0 ≈ 6tSC is obtained. The results reveal that besides the device architecture the underlying charge transport should be also taken into account in designing organic transistors for practical application.

In-situ comparison of Si/High-K and Si/SiO2 interface properties in FD SOI MOSFETs operated at low temperature

Extended Abstracts of the 2007 International Conference on Solid State Devices and Materials, 2007

Detailed measurements of front and back channel characteristics in advanced SOI MOSFETs are used ... more Detailed measurements of front and back channel characteristics in advanced SOI MOSFETs are used to reveal the transport properties at the corresponding Si/High-K and Si/SiO 2 interfaces. Low-temperature operation magnifies the difference between these two interfaces in terms of carrier mobility. The mobility is lower at the Si/High-K interface and increases less rapidly at low temperature, reflecting more complex scattering mechanisms. We also discuss the short-channel effects and the difference between N and P channels.

Impact of a HTO/Al2O3 bi-layer blocking oxide in nitride-trap non-volatile memories

Solid-State Electronics, 2009

In this work, we present an experimental and theoretical study of nitride trap devices with a HTO... more In this work, we present an experimental and theoretical study of nitride trap devices with a HTO/Al2O3 bi-layer blocking oxide. Such SAONOS (Silicon/Alumina/ HTO/Nitride/Oxide/Silicon) devices are compared with standard SONOS (Silicon/HTO/Nitride/Oxide/Silicon) and SANOS (Silicon/Alumina/Nitride/Oxide/Silicon) memories. The role of the different layers (blocking oxide and control gate) is deeply analyzed, focusing on their impact on memory performance and reliability. Then, a semi-analytical model is developed, which provides a good understanding of the physical mechanisms at the origin of program/erase characteristics.

Electrostatic effect of localised charge in dual bit memory cells with discrete traps

The following article, presented at ESSDERC 2004 conference, illustrates the capability of ATLAS ... more

Drift-diffusion and Ballistic Mobility Characterization in Nano CMOS Devices

National audienc

Unexpected impact of germanium content in SiGe bulk PMOSFETs

Solid-State Electronics, 2013

ABSTRACT In this paper, we investigate the impact of silicon–germanium channel on PMOSFETs with T... more ABSTRACT In this paper, we investigate the impact of silicon–germanium channel on PMOSFETs with TiN metal and HfSiON dielectrics gate stack. Performance increase with Ge incorporation in the channel is higher than theoretically expected. Threshold voltage is outstandingly lowered and mobility is highly improved. Poisson–Schrödinger simulations are carried out to interpret the experimental results. Room as well as low temperature mobility measurements and low frequency noise analysis are performed in order to better understand this unforeseen germanium influence. Smaller Coulomb scattering rates are clearly evidenced in SiGe devices, probably explaining the higher mobility.

Low Frequency Noise Performance in TiN/HfO2 Fully Depleted SOI nMOSFET

2006 IEEE international SOI Conferencee Proceedings, 2006

The low frequency noise of TiN/HfO2 fully-depleted SOI nMOSFET is studied for different front and... more

Study of an embedded buried SiGe structure as a mobility booster for fully-depleted SOI MOSFETs at the 10nm node

Solid-State Electronics, 2014

This paper presents mechanical simulations results of an innovative strain transfer structure con... more This paper presents mechanical simulations results of an innovative strain transfer structure consisting in a buried compressive SiGe layer embedded under an ultra-thin buried oxide (BOX). We studied the influence of different dimensions including the active area and determined optimal parameters of the SiGe layer maximizing the strain. We demonstrate a transfer of a tensile stress up to 1.3 GPa in the silicon. Thanks to 3D simulations and the study of stress profiles in the SOI, the electron mobility enhancement is estimated to be about 80% for logic transistors at the 10 nm node. The strain induced in the channel by the edge relaxation of an embedded buried SiGe layer is compared to strained Silicon-On-Insulator (sSOI) wafers and strained nitride layer for Fully Depleted Silicon-On-Insulator (FDSOI).

Revisited approach for the characterization of Gate Induced Drain Leakage

Solid-State Electronics, 2012

ABSTRACT This work presents a critical review and a re-investigation of the electrical characteri... more ABSTRACT This work presents a critical review and a re-investigation of the electrical characterization of Gate Induced Drain Leakage (GIDL) and . The underlying assumptions of the previously proposed extraction methods are exposed and their ability to capture Band-to-Trap mechanisms is discussed. A new approach is introduced to overcome some of the limiting assumptions made by the previous extraction methods. This new approach is benchmarked against the previously proposed ones. The results show that it enables a better extraction of the GIDL parameters compared to the conventional methods, by using the voltage dependency of the activation energy to gain insight in the electric field responsible for Band-to-Band Tunneling in the device. Finally, the experimental application of this new approach is carried out on cold process FDSOI MOSFET and confirms the ability of this new method to quantify the impact of trap assisted tunneling on GIDL.

Comparative study of circuit perspectives for multi-gate structures at sub-10nm node

Solid-State Electronics, 2012

This work presents a comparative study between planar and vertical (FinFETs) multi-gate structure... more This work presents a comparative study between planar and vertical (FinFETs) multi-gate structures for 2017 ITRS specifications circuit perspectives. Propagation delays are simulated for inverter chain and NAND gate chain. Finally, the impact of the width is investigated on several design rules for FinFETs configurations.

Bardeen's approach for tunneling evaluation in MOS structures

Solid-State Electronics, 2002

This work is a presentation of the so-called “Bardeen's approach” formalism for tunneling. T... more This work is a presentation of the so-called “Bardeen's approach” formalism for tunneling. The way to use it for the modeling of tunnel current in MOS structure is also discussed. The theoretical background of this formalism is presented in an understandable way, and compared with other approaches. Then, an original method to use it is also proposed, which allows both numerical and analytical calculations.

Carrier mobility in advanced CMOS devices with metal gate and HfO2 gate dielectric

Solid-State Electronics, 2003

ABSTRACT Advanced channel N and P MOSFETs with HfO2 gate dielectric and metal gate have been fabr... more ABSTRACT Advanced channel N and P MOSFETs with HfO2 gate dielectric and metal gate have been fabricated and exhibit high performance. The effective mobility has been characterized at various temperatures for NMOS and PMOS devices. The electron mobility is lower than in SiO2, whereas the hole mobility is relatively unaffected at room temperature but also degraded at low temperatures. The mobility degradation after constant voltage stress suggests a more important Coulomb scattering contribution to mobility as compared to SiO2.

Study of stress induced leakage current by using high resolution measurements

Microelectronics Reliability, 1999

A thorough characterization of stress-induced leakage currents (SILCs) for a 10nm-thick oxide, by... more A thorough characterization of stress-induced leakage currents (SILCs) for a 10nm-thick oxide, by using the floating-gate technique, is presented. The obtained current is modeled by a volume-limited conduction mechanism. Experimental and model suggest that SILC conduction mechanism is the same in thin as well as in thick oxides.

Wear-out, breakdown occurrence and failure detection in 18–25 Å ultrathin oxides

Microelectronics Reliability, 2001

In this paper, a comprehensive description of the ultrathin oxide failure evolution is presented.... more In this paper, a comprehensive description of the ultrathin oxide failure evolution is presented. For sub-25 Å, Hard BD is no longer hard. A complete description of the novel failure manifestation (progressive breakdown) is done. Associated wear-out is modelled and a physical mechanism is proposed. Finally, the relevance of the failure definition is discussed. It is a crucial point, to

Charge trapping in SiO2/HfO2/TiN gate stack

Microelectronics Reliability, 2003

ABSTRACT Further scaling of CMOS technologies will require the use of high K gate dielectrics in ... more ABSTRACT Further scaling of CMOS technologies will require the use of high K gate dielectrics in order to keep a sufficiently low leakage current. The electrical properties of these new materials, especially in terms of interface quality, mobility and reliability can be regarded as a major concern. In this work, we have studied charge trapping in HfO2/SiO2 gate dielectric stacks using CVS and CCS with gate and drain currents vs gate voltage measurements. We found positive charge trapping for gate injection and negative charge trapping for substrate injection. We also gained more insight into the influence on charge trapping of the buffer SiO2 layer.