Papers by Frank Schirrmeister
Proceedings of the International Symposium on Memory Systems, Oct 2, 2023
ABSTRACT The possibilities of VLSI technology grow by a factor of 100 per decade. In parallel, de... more ABSTRACT The possibilities of VLSI technology grow by a factor of 100 per decade. In parallel, design efficiency has been increased only by a factor 30 per decade, so major problems in the development of complex systems have been shifted from controlling new technologies to the management of the design process itself. Classical design methods tend to fail for VLSI circuits with increasing complexity, often due to communication problems. To avoid redesigns, the adoption of methods of neighbour discipline software engineering seems to be a good choice. This paper discusses the influence of these methods on the quality of VLSI designs in terms of errors per design and costs per error detection. Statements and experiences are based on statistical data collected during several developments of complex systems including VLSI components
Proceedings of SPIE, Nov 4, 1993
ABSTRACT The phasecorrelation algorithm--as a method for motion estimation--is an important compo... more ABSTRACT The phasecorrelation algorithm--as a method for motion estimation--is an important component of an HDTV system. The advantage of hardware realization of this algorithm for efficient real time processing--in opposite to blockmatching--is the possibility to process multiple pixels per system clock cycle. A suitable partition for a phasecorrelation chipset is going to be proposed. To minimize the motion estimators physical volume all external components except RAMs, have been integrated on three specialized chips.
Elsevier eBooks, 2013
When planning the development of modern embedded systems, hardware and software cannot be conside... more When planning the development of modern embedded systems, hardware and software cannot be considered independently. Over the last two decades chip and system complexity has seen an enormous amount of growth, while more and more system functionality has moved from dedicated hardware implementation into software executing on general-purposed embedded processors. By 2010 the development effort for software had outgrown the development efforts for hardware, and the complexity trend continues in favor of software. Traditional design techniques such as independent hardware and software design are being challenged due to heterogeneous models and applications being integrated to create a complex system on chip. Using proper techniques of hardware-software codesign, designers consider the trade-offs in the way hardware and software components of a system work together to exhibit a specified behavior, given a set of performance goals and technology. This chapter will cover these topics.
Proceedings of SPIE, Feb 17, 1995
A solution for real-time compression of digital YCRCB video data to an MPEG-1 video data stream h... more A solution for real-time compression of digital YCRCB video data to an MPEG-1 video data stream has been developed. As an additional option, motion JPEG and video telephone streams (H.261) can be generated. For MPEG-1, up to two bidirectional predicted images are supported. The required computational power for motion estimation and DCT/IDCT, memory size and memory bandwidth have been the main challenges. The design uses fast-page-mode memory accesses and requires only one single 80 ns EDO-DRAM with 256 X 16 organization for video encoding. This can be achieved only by using adequate access and coding strategies. The architecture consists of an input processing and filter unit, a memory interface, a motion estimation unit, a motion compensation unit, a DCT unit, a quantization control, a VLC unit and a bus interface. For using the available memory bandwidth by the processing tasks, a fixed schedule for memory accesses has been applied, that can be interrupted for asynchronous events. The motion estimation unit implements a highly sophisticated hierarchical search strategy based on block matching. The DCT unit uses a separated fast-DCT flowgraph realized by a switchable hardware unit for both DCT and IDCT operation. By appropriate multiplexing, only one multiplier is required for: DCT, quantization, inverse quantization, and IDCT. The VLC unit generates the video-stream up to the video sequence layer and is directly coupled with an intelligent bus-interface. Thus, the assembly of video, audio and system data can easily be performed by the host computer. Having a relatively low complexity and only small requirements for DRAM circuits, the developed solution can be applied to low-cost encoding products for consumer electronics.
In this paper, we describe the challenges users face for software development on Systems on Chip ... more In this paper, we describe the challenges users face for software development on Systems on Chip (SoC) involving multiple cores. We will briefly review the trends and challenges for MPSoC design and will derive from them the resulting requirements. We will then discuss briefly the required exploration tools and close with an analysis of which type of providers will be able to provide appropriate solutions to the MPSoC challenge.
Abstract System design is moving from a trial-and-error manual process towards a more rigorous an... more Abstract System design is moving from a trial-and-error manual process towards a more rigorous and tool-supported approach. The driving function for this move is the need to develop new products quickly, correctly and inexpensively. Time-to-market of four to six months are not uncommon today for some electronic systems. At the same time, there is a need to leverage maximally what deep sub-micron (DSM) technology has to offer to compete. Hence, an approach that has design re-use as its main goal has great potential ...
Springer eBooks, 2001
As wireless, multimedia, communications, and other embedded systems converge and increase in capa... more As wireless, multimedia, communications, and other embedded systems converge and increase in capability, the task of system and implementation designers to efficiently design and verify embedded systems grows exponentially. Overall, the compounding complexities of chip design, silicon process, SoC system context and complete end to end verification are presenting new system design challenges. They have focused attention on tools supporting hardware-software co-design using Intellectual Property (IP) based design techniques at the system level Using methodologies and tools described in this paper, users will dramatically increase predictability and productivity of their SOC hardware/software design flows enabled by advanced reuse of system level IP. The techniques described in this paper will also enable efficient communication between system level and implementation level design teams
Recently there has been a rapid increase in the integration level of embedded systems for use in ... more Recently there has been a rapid increase in the integration level of embedded systems for use in communications and multimedia products. This higher level of integration has focused attention on significant gaps in the methodology and the technology for design of complex system-chips and chipsets including problems with design environments. These gaps have also lead to the emergence of the market place for virtual components (also often referred to as “intellectual property”) for hardware and software to address the challenges of reuse of pre-verified virtual components
IEEE Computer, Mar 1, 2002
The phasecorrelation algorithm - as a method for motion vector estimation - is an important compo... more The phasecorrelation algorithm - as a method for motion vector estimation - is an important component of todays HDTV systems. Many picture processing methods like predictive filters for picture coding or standards conversion are based on motion vectors. This paper describes a motion vector estimator using phasecorrelation, which works in combination with blockmatching to compress video data. The result is a bandwidth-reduction for transmitting HDTV video signals. The advantage of a hardware realization of phasecorrelation for efficient real time processing - in opposite to blockmatching - is the possibility to process multiple pixels per system clock cycle. So phasecorrelation represents a useful method to reduce hardware effort of blockmatching systems by using motion vectors, estimated by phasecorrelation, as a suggestion for blockmatching. In this case blockmatching doesn't need to handle full searchranges but only small searchranges centred around the suggested motion vectors of phase-correlation. A suitable partition for a phasecorrelation chipset is proposed. To minimize the motion estimators physical volume all external components except RAM's have been integrated on three specialized VLSI-circuits. Several available RAMs are supported (dual or single-ported).
IEEE Communications Magazine, Jun 1, 2010
ABSTRACT Over the last decade, a new reality has set in for the semiconductor industry. In a vari... more ABSTRACT Over the last decade, a new reality has set in for the semiconductor industry. In a variety of application domains like wireless, multimedia, networking, and automotive, it has become more and more difficult to provide silicon solutions without the associated software executing on the hardware. Not only has software become the key functional differentiator in many areas; its development cycle now determines the overall project success. Market research firm International Business Strategies, Inc. claims that today at 90 nm the typical overall SoC-related development effort for software has already surpassed the effort for hardware. For 45 nm designs in the year 2011, IBS projects that less than 40 percent of the overall development efforts will be spent on hardware. Given the ever growing levels of complexity, traditional approaches to developing embedded software are failing to meet the challenge; a new era of software development has begun in which the majority of embedded software is developed with virtual prototypes, in contrast to traditional software development on hardware boards.
Elsevier eBooks, 2013
This chapter will introduce the concepts of multicore related issues, while the subsequent chapte... more This chapter will introduce the concepts of multicore related issues, while the subsequent chapters will go into further details. We will start with a general analysis of how electronic design trends lead to multicore hardware-software architectures as the only viable solution addressing consumer requirements on cost, performance and power. We will then categorize multicore architecture concepts by processing and communication requirements and show how different processing techniques combine to form multicore architectures that address the specific needs of different application domains. Special attention will be given to the programmability of the different hardware architectures and the impact that hardware has on software. We will close the chapter with a brief review of existing hardware architectures available on the market, as well as a brief discussion about programming models capable of expressing parallel functionality, which can then be mapped into multiple processor cores.
The phasecorrelation algorithm - as a method for motion estimation - is a key component of todays... more The phasecorrelation algorithm - as a method for motion estimation - is a key component of todays TV and tomorrows HDTV-systems. One advantage of hardware realization of this algorithm for efficient real time processing - in opposite to blockmatching - is the possibility to process multiple pixels per system clock cycle. A suitable partition using three different VLSI-circuits to perform
SAE International Journal of Passenger Cars - Electronic and Electrical Systems, Apr 20, 2009
The case for developing and using virtual platforms (VPs) has now been made. If developers of com... more The case for developing and using virtual platforms (VPs) has now been made. If developers of complex HW/SW systems are not using VPs for their current design, complexity of next generation designs demands for their adoption. In addition, the users of these complex systems are asking either for virtual or real platforms in order to develop and validate the software that runs on them, in context with the hardware that is used to deliver some of the functionality. Debugging the erroneous interactions of events and state in a modern platform when things go wrong is hard enough on a VP; on a real platform (such as an emulator or FPGA-based prototype) it can become impossible unless a new level of sophistication is offered. The priority now is to ensure that the capabilities of these platforms meet the requirements of every application domain for electronics and software-based product design. And to ensure that all the use cases are satisfied. A key requirement is to keep pace with Moore's Law and the ever increasing embedded SW complexity by providing novel simulation technologies in every product release. This paper summarizes a special session focused on the latest applications and latest use cases for VPs. It gives an overview of where this technology is going and the impact on complex system design and verification.
The evolution to Manycore platforms is real, both in the High-Performance Computing domain and in... more The evolution to Manycore platforms is real, both in the High-Performance Computing domain and in embedded systems. If we start with ten or more cores, we can see the evolution to many tens of cores and to platforms with 100 or more occurring in the next few years. These platforms are heterogeneous, homogeneous, or a mixture of subsystems of both types, both relatively generic and quite application-specific. They are applied to many different application areas. When we consider the design, verification, software development and debugging requirements for applications on these platforms, the need for virtual platform technologies for Manycore systems grows quickly as the systems evolve. As we move to Manycore, the key issue is simulation speed, and trying to keep pace with the target complexity using host-based simulation is a major challenge. New Instruction Set Simulation technologies, such as compiled, JIT, DBT, sampling, abstract, hybrid and parallel have all emerged in the last few years to match the growth in complexity and requirements. At the same time, we have seen consolidation in the virtual platform industrial sector, leading to some concerns about whether the market can support the required continued development of innovations to give the needed performance. This special session deals with Manycore virtual platforms from several different perspectives, highlighting new research approaches for high speed simulation, tool and IP marketing opportunities, as well as real life virtual platform needs of industrial end users. I.
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Papers by Frank Schirrmeister