International journal of imaging and robotics, May 22, 2018
Demand for high quality video is growing exponentially especially with the H.264/AVC and the H.26... more Demand for high quality video is growing exponentially especially with the H.264/AVC and the H.265/HEVC standards which have placed a significant emphasis on computational power of the processors. In both standards, the motion estimation block takes very intensive processing. That is why recently Graphics Processing Units have emerged as a viable target for speeding such applications by harnessing parallelism. This paper describes our GPU Full Search Motion Estimation implementation and presents novel methods of optimization, allowing to manipulate the GPU in a flexible way. These optimization methods can provide high performance video encoder where the speed up reaches about 90.
With the rapid development of multimedia technologies and network communication, the parallel arc... more With the rapid development of multimedia technologies and network communication, the parallel architecture such as the Graphic Processing Unit (GPU) is introduced in high-performance computing. But, how to program this GPU and how to obtain the best execution time remains usually an art. In this paper, a search study is performed on the Thread and the Block number that leads to a Prediction Unit of 64×64 (PU64) computation in the High Efficiency Video Coding (HEVC). It is proposed through the Compute Unified Device Architecture (CUDA). This method is described to optimize the GPU execution time. Experimental results show that the best Grid topology chosen to run the GPU kernel is obtained for 128 Block and 32 Thread. This proposed repartition gives the minimum GPU execution time compared to the CPU one, where the speed-up obtained here is around 50%.
In order to speed up video coding efficiency such as H.264/AVC and H265/HEVC, we propose in this ... more In order to speed up video coding efficiency such as H.264/AVC and H265/HEVC, we propose in this paper a parallel approach of full search (FS) algorithm for motion estimation on Graphic Processor Unit (GPU). We implemented the traditional sequential FS algorithm for motion estimation to computing unified device architecture (CUDA) optimizing memory usage, taking full ad-vantage of the powerful parallel computing capability to speed up FS motion estimation. Experimental results show that our implementation on CUDA demonstrates substantial improvement up to 48 times than CPU counterpart available and can effectively speed up the FS for motion estimation
International journal of imaging and robotics, 2017
Reducing the Sum of Absolute Differences (SAD) computational time, reduces the motion estimation ... more Reducing the Sum of Absolute Differences (SAD) computational time, reduces the motion estimation (ME) time, which leads to the decrease of all the High-Efficiency Video Coding (HEVC) time. This paper proposes two parallel implementation of the SAD algorithm of the HEVC Motion Estimation (ME), on Fermi and Kepler GPUs (Graphic Processing Unit) generations. Both implementations are computed with Compute Unified Device Architecture (CUDA). A comparison of the obtained results, on those two successive GPU generations, are given and discussed, for some test blocks, from 4x4 to 64x64.The investigational results show that the speedup reaches a maximum at the biggest block size used for HEVC encoder, regardless the system GPU card used. The GPU performances for 64x64-block size are enhanced, compared to the results obtained on CPU, by around 50% for the Fermi GPU system and by 25% for the Kepler one. By comparing the results on GPU, for each architectures, we concluded that the GPU frequenc...
High Efficiency Video Coding (HEVC) doubles the compression rates over the previous H.264 standar... more High Efficiency Video Coding (HEVC) doubles the compression rates over the previous H.264 standard for the same video quality. To improve the coding efficiency, HEVC adopts the hierarchical quadtree structured Coding Unit (CU). However, the computational complexity significantly increases due to the full search for Rate-Distortion Optimization (RDO) to find the optimal Coding Tree Unit (CTU) partition. Here, this paper proposes a deep learning model to predict the HEVC CU partition at inter-mode, instead of brute-force RDO search. To learn the learning model, a large-scale database for HEVC inter-mode is first built. Second, to predict the CU partition of HEVC, we propose as a model a combination of a Convolutional Neural Network (CNN) and a Long Short-Term Memory (LSTM) network. The simulation results prove that the proposed scheme can achieve a best compromise between complexity reduction and RD performance, compared to existing approaches.
The high performance of the high efficiency video coding (HEVC) video standard makes it more suit... more The high performance of the high efficiency video coding (HEVC) video standard makes it more suitable for high-definition resolutions. Nevertheless, this encoding performance is coupled with a tremendous encoding complexity compared to the earlier H264 video codec. The HEVC complexity is mainly a return to the motion estimation (ME) module that represents the important part of encoding time which makes several researches turn around the optimization of this module. Some works are interested in hardware solutions exploiting the parallel processing of FPGA, GPU, or other multicore architectures, and other works are focused on software optimizations by inducing fast mode decision algorithms. In this context, this article proposes a fast HEVC encoder configuration to speed up the encoding process. The fast configuration uses different options such as the early skip detection (ESD), the early CU termination (ECU), and the coded block flag (CBF) fast method (CFM) modes. Regarding the algorithm of ME, the diamond search (DS) is used in the encoding process through several video resolutions. A time saving around 46.75% is obtained with an acceptable distortion in terms of video quality and bitrate compared to the reference test model HM.16.2. Our contribution is compared to other works for better evaluation.
Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering), 2019
Background: Advances in video compression technology have been driven by everincreasing processin... more Background: Advances in video compression technology have been driven by everincreasing processing power available in software and hardware. Methods: The emerging High-Efficiency Video Coding (HEVC) standard aims to provide a doubling in coding efficiency with respect to the H.264/AVC high profile, delivering the same video quality at half the bit rate. Results: Thus, the results show high computational complexity. In both standards, the motion estimation block presents a significant challenge in clock latency since it consumes more than 40% of the total encoding time. For these reasons, we proposed an optimized implementation of this algorithm on a low-cost NVIDIA GPU developed with CUDA language. Conclusion: This optimized implementation can provide high-performance video encoder where the speed reaches about 85.
As video processing technologies continue to rise quicker than central processing unit (CPU) perf... more As video processing technologies continue to rise quicker than central processing unit (CPU) performance in complexity and image resolution, data-parallel computing methods will be even more important. In fact, the high-performance, data-parallel architecture of modern graphics processing unit (GPUs) can minimise execution times by orders of magnitude or more. However, creating an optimal GPU implementation not only needs converting sequential implementation of algorithms into parallel ones but, more importantly, needs cautious balancing of the GPU resources. It requires also an understanding of the bottlenecks and defect caused by memory latency and code computing. The defiance is even greater when an implementation exceeds the GPU resources. In this study, the authors discuss the parallelisation and memory optimisation strategies of a computer vision application for motion estimation using the NVIDIA compute unified device architecture (CUDA). It addresses optimisation techniques for algorithms that surpass the GPU resources in either computation or memory resources for CUDA architecture. The proposed implementation reveals a substantial improvement in both speed up (SU) and peak signal-to-noise ratio (PSNR). Indeed, the implementation is up to 50 times faster than the CPU counterpart. It also provides an increase in PSNR of the coded test sequence up to 8 dB.
The new High-Efficiency Video Coding (HEVC) standard doubles the video compression ratio compared... more The new High-Efficiency Video Coding (HEVC) standard doubles the video compression ratio compared to the previous H.264/AVC at the same video quality and without any degradation. However, this important performance is achieved by increasing the encoder computational complexity. That's why HEVC complexity is a crucial subject. The most time consuming and the most intensive computing part of HEVC is the motion estimation based principally on the sum of absolute differences (SAD) or the sum of square differences (SSD) algorithms. For these reasons, the authors proposed an implementation of these algorithms on a low cost NVIDIA GPU (graphics processing unit) using the Fermi architecture developed with Compute Unified Device Architecture language. The proposed algorithm is based on the parallel-difference and the parallel-reduction process. The investigational results show a significant speed-up in terms of execution time for most 64 × 64 pixel blocks. In fact, the proposed parallel algorithm permits a significant reduction in the execution time that reaches up to 56.17 and 30.4%, compared to the CPU, for SAD and SSD algorithms, respectively. This improvement proves that parallelising the algorithm with the new proposed reduction process for the Fermi-GPU generation leads to better results. These findings are based on a static study that determines the PU percentage utilisation for each dimension in the HEVC. This study shows that the larger PUs are the most utilised in temporal levels 3 and 4, which attain 84.56% for class E. This improvement is accompanied by an average peak signal-to-noise ratio loss of 0.095 dB and a decrease of 0.64% in terms of BitRate.
Journal of Algorithms & Computational Technology, 2017
With the advancement in the device technology and parallel architecture, field-programmable gate ... more With the advancement in the device technology and parallel architecture, field-programmable gate arrays (FPGAs) can well perform the speech processing operation. FPGAs have very impressive results, despite their low operating frequency, by completely extracting the parallelism. Nevertheless, recent central processing unit and graphic processing unit (GPU) have also an inherent feature for high performance. In fact, recent GPUs enable dramatic increases in computing performance by harnessing great number of cores. In this context, we seek to analyze the performance of the linear prediction coding algorithm implementation on two different platforms: one based on the GPU NVIDIA GeForce GTX 480 and another on the FPGA Spartan-6. Subsequently, we try to apply several optimization strategies on those platforms. The experimental results highlight the relative robustness or weakness of both these platforms. The tests prove that, for several samples, GPU manages speedups of up to 4Â compared to the FPGA and around 48Â compared to a sequential execution.
2016 International Image Processing, Applications and Systems (IPAS), 2016
In this paper, a fast configuration for Motion Estimation (ME) is described in order to reduce th... more In this paper, a fast configuration for Motion Estimation (ME) is described in order to reduce the computational time of the new High Efficient Video Coding (HEVC). This configuration uses the Coded Block Flag (CBF) Fast Method (CFM), the Early Coding Unit (CU) termination (ECU) and the Early Skip Detection (ESD) modes. The Diamond Pattern is used as a search algorithm for ME in the encoding process. Compared to the latest original reference software test model (HM) 16.2 of the HEVC, experimental results had showed that the complexity is reduced, in average, by 56.75% with a small bit-rate and PSNR degradation.
In this work, we introduce real time image processing techniques using modern programmable Graphi... more In this work, we introduce real time image processing techniques using modern programmable Graphic Processing Units GPU. GPU are SIMD (Single Instruction, Multiple Data) device that is inherently data-parallel. By utilizing NVIDIA new GPU programming framework, "Compute Unified Device Architecture" CUDA as a computational resource, we realize significant acceleration in image processing algorithm computations. We show that a range of computer vision algorithms map readily to CUDA with significant performance gains. Specifically, we demonstrate the efficiency of our approach by a parallelization and optimization of image processing, Morphology applications and image integral.
ABSTRACT Face detection is an important aspect for various domains such as: biometrics, video sur... more ABSTRACT Face detection is an important aspect for various domains such as: biometrics, video surveillance and human computer interaction. Generally a generic face processing system includes a face detection, or recognition step, as well as tracking and rendering phase. In this paper, we develop a real-time and robust face detection implementation based on GPU component. Face detection is performed by adapting the Viola and Jones algorithm. We have developed and designed optimized several parallel implementations of these algorithms based on graphics processors GPU using CUDA (Compute Unified Device Architecture) description.
ABSTRACT Face detection in a fixed image without special hypothesis is a difficult problem due to... more ABSTRACT Face detection in a fixed image without special hypothesis is a difficult problem due to the high variability of the shape to detect. Many techniques of detection and face recognition have been developed in recent years and many of which are very efficient. Among these methods, we find the method of Viola and Jones were studied in this work. The aim of our work is to study this method to implement on the CPU with C / C + +, then acceleration was presented with OpenCV. Subsequently, a second implementation in FPGA was presented Keywords— Face detection, method of Viola/Jones, C/C++, OpenCV, FPGA. I. INTRODUCTION Face detection is a new computer technology that determines the locations and sizes of human faces in images. It detects facial features and ignores anything else, such as buildings, trees, bodies and any device other than the face and so on [4] .This technology is used in many fields such as biometrics for identification and recognition face, it is also used in video surveillance systems and many digital cameras use the latest face detection for autofocus. Our work is divided into three parts: In the first part we present the method of Viola and Jones face detection. Subsequently a second part deals with the face detection on C/C++. The acceleration with OpenCV is presented later, a second implementation in FPGA was presented. Finally, we conclude the paper.
2014 Global Summit on Computer & Information Technology (GSCIT), 2014
Discrete wavelet transform (DWT) has diverse applications in signal and image processing fields. ... more Discrete wavelet transform (DWT) has diverse applications in signal and image processing fields. In this paper, we have implemented the lifting “Cohen-Daubechies-Feauveau 9/7” algorithm on a low cost NVIDIA's GPU (Graphics Processing Unit) with MatLab to achieve speedup in computation. The efficiency of our GPU based implementation is measured and compared with CPU based algorithms. Our investigational results with GPU show performance enhancement over a factor of 1.82 compared with CPU for an image of size 4096×4096 pixels.
International journal of imaging and robotics, May 22, 2018
Demand for high quality video is growing exponentially especially with the H.264/AVC and the H.26... more Demand for high quality video is growing exponentially especially with the H.264/AVC and the H.265/HEVC standards which have placed a significant emphasis on computational power of the processors. In both standards, the motion estimation block takes very intensive processing. That is why recently Graphics Processing Units have emerged as a viable target for speeding such applications by harnessing parallelism. This paper describes our GPU Full Search Motion Estimation implementation and presents novel methods of optimization, allowing to manipulate the GPU in a flexible way. These optimization methods can provide high performance video encoder where the speed up reaches about 90.
With the rapid development of multimedia technologies and network communication, the parallel arc... more With the rapid development of multimedia technologies and network communication, the parallel architecture such as the Graphic Processing Unit (GPU) is introduced in high-performance computing. But, how to program this GPU and how to obtain the best execution time remains usually an art. In this paper, a search study is performed on the Thread and the Block number that leads to a Prediction Unit of 64×64 (PU64) computation in the High Efficiency Video Coding (HEVC). It is proposed through the Compute Unified Device Architecture (CUDA). This method is described to optimize the GPU execution time. Experimental results show that the best Grid topology chosen to run the GPU kernel is obtained for 128 Block and 32 Thread. This proposed repartition gives the minimum GPU execution time compared to the CPU one, where the speed-up obtained here is around 50%.
In order to speed up video coding efficiency such as H.264/AVC and H265/HEVC, we propose in this ... more In order to speed up video coding efficiency such as H.264/AVC and H265/HEVC, we propose in this paper a parallel approach of full search (FS) algorithm for motion estimation on Graphic Processor Unit (GPU). We implemented the traditional sequential FS algorithm for motion estimation to computing unified device architecture (CUDA) optimizing memory usage, taking full ad-vantage of the powerful parallel computing capability to speed up FS motion estimation. Experimental results show that our implementation on CUDA demonstrates substantial improvement up to 48 times than CPU counterpart available and can effectively speed up the FS for motion estimation
International journal of imaging and robotics, 2017
Reducing the Sum of Absolute Differences (SAD) computational time, reduces the motion estimation ... more Reducing the Sum of Absolute Differences (SAD) computational time, reduces the motion estimation (ME) time, which leads to the decrease of all the High-Efficiency Video Coding (HEVC) time. This paper proposes two parallel implementation of the SAD algorithm of the HEVC Motion Estimation (ME), on Fermi and Kepler GPUs (Graphic Processing Unit) generations. Both implementations are computed with Compute Unified Device Architecture (CUDA). A comparison of the obtained results, on those two successive GPU generations, are given and discussed, for some test blocks, from 4x4 to 64x64.The investigational results show that the speedup reaches a maximum at the biggest block size used for HEVC encoder, regardless the system GPU card used. The GPU performances for 64x64-block size are enhanced, compared to the results obtained on CPU, by around 50% for the Fermi GPU system and by 25% for the Kepler one. By comparing the results on GPU, for each architectures, we concluded that the GPU frequenc...
High Efficiency Video Coding (HEVC) doubles the compression rates over the previous H.264 standar... more High Efficiency Video Coding (HEVC) doubles the compression rates over the previous H.264 standard for the same video quality. To improve the coding efficiency, HEVC adopts the hierarchical quadtree structured Coding Unit (CU). However, the computational complexity significantly increases due to the full search for Rate-Distortion Optimization (RDO) to find the optimal Coding Tree Unit (CTU) partition. Here, this paper proposes a deep learning model to predict the HEVC CU partition at inter-mode, instead of brute-force RDO search. To learn the learning model, a large-scale database for HEVC inter-mode is first built. Second, to predict the CU partition of HEVC, we propose as a model a combination of a Convolutional Neural Network (CNN) and a Long Short-Term Memory (LSTM) network. The simulation results prove that the proposed scheme can achieve a best compromise between complexity reduction and RD performance, compared to existing approaches.
The high performance of the high efficiency video coding (HEVC) video standard makes it more suit... more The high performance of the high efficiency video coding (HEVC) video standard makes it more suitable for high-definition resolutions. Nevertheless, this encoding performance is coupled with a tremendous encoding complexity compared to the earlier H264 video codec. The HEVC complexity is mainly a return to the motion estimation (ME) module that represents the important part of encoding time which makes several researches turn around the optimization of this module. Some works are interested in hardware solutions exploiting the parallel processing of FPGA, GPU, or other multicore architectures, and other works are focused on software optimizations by inducing fast mode decision algorithms. In this context, this article proposes a fast HEVC encoder configuration to speed up the encoding process. The fast configuration uses different options such as the early skip detection (ESD), the early CU termination (ECU), and the coded block flag (CBF) fast method (CFM) modes. Regarding the algorithm of ME, the diamond search (DS) is used in the encoding process through several video resolutions. A time saving around 46.75% is obtained with an acceptable distortion in terms of video quality and bitrate compared to the reference test model HM.16.2. Our contribution is compared to other works for better evaluation.
Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering), 2019
Background: Advances in video compression technology have been driven by everincreasing processin... more Background: Advances in video compression technology have been driven by everincreasing processing power available in software and hardware. Methods: The emerging High-Efficiency Video Coding (HEVC) standard aims to provide a doubling in coding efficiency with respect to the H.264/AVC high profile, delivering the same video quality at half the bit rate. Results: Thus, the results show high computational complexity. In both standards, the motion estimation block presents a significant challenge in clock latency since it consumes more than 40% of the total encoding time. For these reasons, we proposed an optimized implementation of this algorithm on a low-cost NVIDIA GPU developed with CUDA language. Conclusion: This optimized implementation can provide high-performance video encoder where the speed reaches about 85.
As video processing technologies continue to rise quicker than central processing unit (CPU) perf... more As video processing technologies continue to rise quicker than central processing unit (CPU) performance in complexity and image resolution, data-parallel computing methods will be even more important. In fact, the high-performance, data-parallel architecture of modern graphics processing unit (GPUs) can minimise execution times by orders of magnitude or more. However, creating an optimal GPU implementation not only needs converting sequential implementation of algorithms into parallel ones but, more importantly, needs cautious balancing of the GPU resources. It requires also an understanding of the bottlenecks and defect caused by memory latency and code computing. The defiance is even greater when an implementation exceeds the GPU resources. In this study, the authors discuss the parallelisation and memory optimisation strategies of a computer vision application for motion estimation using the NVIDIA compute unified device architecture (CUDA). It addresses optimisation techniques for algorithms that surpass the GPU resources in either computation or memory resources for CUDA architecture. The proposed implementation reveals a substantial improvement in both speed up (SU) and peak signal-to-noise ratio (PSNR). Indeed, the implementation is up to 50 times faster than the CPU counterpart. It also provides an increase in PSNR of the coded test sequence up to 8 dB.
The new High-Efficiency Video Coding (HEVC) standard doubles the video compression ratio compared... more The new High-Efficiency Video Coding (HEVC) standard doubles the video compression ratio compared to the previous H.264/AVC at the same video quality and without any degradation. However, this important performance is achieved by increasing the encoder computational complexity. That's why HEVC complexity is a crucial subject. The most time consuming and the most intensive computing part of HEVC is the motion estimation based principally on the sum of absolute differences (SAD) or the sum of square differences (SSD) algorithms. For these reasons, the authors proposed an implementation of these algorithms on a low cost NVIDIA GPU (graphics processing unit) using the Fermi architecture developed with Compute Unified Device Architecture language. The proposed algorithm is based on the parallel-difference and the parallel-reduction process. The investigational results show a significant speed-up in terms of execution time for most 64 × 64 pixel blocks. In fact, the proposed parallel algorithm permits a significant reduction in the execution time that reaches up to 56.17 and 30.4%, compared to the CPU, for SAD and SSD algorithms, respectively. This improvement proves that parallelising the algorithm with the new proposed reduction process for the Fermi-GPU generation leads to better results. These findings are based on a static study that determines the PU percentage utilisation for each dimension in the HEVC. This study shows that the larger PUs are the most utilised in temporal levels 3 and 4, which attain 84.56% for class E. This improvement is accompanied by an average peak signal-to-noise ratio loss of 0.095 dB and a decrease of 0.64% in terms of BitRate.
Journal of Algorithms & Computational Technology, 2017
With the advancement in the device technology and parallel architecture, field-programmable gate ... more With the advancement in the device technology and parallel architecture, field-programmable gate arrays (FPGAs) can well perform the speech processing operation. FPGAs have very impressive results, despite their low operating frequency, by completely extracting the parallelism. Nevertheless, recent central processing unit and graphic processing unit (GPU) have also an inherent feature for high performance. In fact, recent GPUs enable dramatic increases in computing performance by harnessing great number of cores. In this context, we seek to analyze the performance of the linear prediction coding algorithm implementation on two different platforms: one based on the GPU NVIDIA GeForce GTX 480 and another on the FPGA Spartan-6. Subsequently, we try to apply several optimization strategies on those platforms. The experimental results highlight the relative robustness or weakness of both these platforms. The tests prove that, for several samples, GPU manages speedups of up to 4Â compared to the FPGA and around 48Â compared to a sequential execution.
2016 International Image Processing, Applications and Systems (IPAS), 2016
In this paper, a fast configuration for Motion Estimation (ME) is described in order to reduce th... more In this paper, a fast configuration for Motion Estimation (ME) is described in order to reduce the computational time of the new High Efficient Video Coding (HEVC). This configuration uses the Coded Block Flag (CBF) Fast Method (CFM), the Early Coding Unit (CU) termination (ECU) and the Early Skip Detection (ESD) modes. The Diamond Pattern is used as a search algorithm for ME in the encoding process. Compared to the latest original reference software test model (HM) 16.2 of the HEVC, experimental results had showed that the complexity is reduced, in average, by 56.75% with a small bit-rate and PSNR degradation.
In this work, we introduce real time image processing techniques using modern programmable Graphi... more In this work, we introduce real time image processing techniques using modern programmable Graphic Processing Units GPU. GPU are SIMD (Single Instruction, Multiple Data) device that is inherently data-parallel. By utilizing NVIDIA new GPU programming framework, "Compute Unified Device Architecture" CUDA as a computational resource, we realize significant acceleration in image processing algorithm computations. We show that a range of computer vision algorithms map readily to CUDA with significant performance gains. Specifically, we demonstrate the efficiency of our approach by a parallelization and optimization of image processing, Morphology applications and image integral.
ABSTRACT Face detection is an important aspect for various domains such as: biometrics, video sur... more ABSTRACT Face detection is an important aspect for various domains such as: biometrics, video surveillance and human computer interaction. Generally a generic face processing system includes a face detection, or recognition step, as well as tracking and rendering phase. In this paper, we develop a real-time and robust face detection implementation based on GPU component. Face detection is performed by adapting the Viola and Jones algorithm. We have developed and designed optimized several parallel implementations of these algorithms based on graphics processors GPU using CUDA (Compute Unified Device Architecture) description.
ABSTRACT Face detection in a fixed image without special hypothesis is a difficult problem due to... more ABSTRACT Face detection in a fixed image without special hypothesis is a difficult problem due to the high variability of the shape to detect. Many techniques of detection and face recognition have been developed in recent years and many of which are very efficient. Among these methods, we find the method of Viola and Jones were studied in this work. The aim of our work is to study this method to implement on the CPU with C / C + +, then acceleration was presented with OpenCV. Subsequently, a second implementation in FPGA was presented Keywords— Face detection, method of Viola/Jones, C/C++, OpenCV, FPGA. I. INTRODUCTION Face detection is a new computer technology that determines the locations and sizes of human faces in images. It detects facial features and ignores anything else, such as buildings, trees, bodies and any device other than the face and so on [4] .This technology is used in many fields such as biometrics for identification and recognition face, it is also used in video surveillance systems and many digital cameras use the latest face detection for autofocus. Our work is divided into three parts: In the first part we present the method of Viola and Jones face detection. Subsequently a second part deals with the face detection on C/C++. The acceleration with OpenCV is presented later, a second implementation in FPGA was presented. Finally, we conclude the paper.
2014 Global Summit on Computer & Information Technology (GSCIT), 2014
Discrete wavelet transform (DWT) has diverse applications in signal and image processing fields. ... more Discrete wavelet transform (DWT) has diverse applications in signal and image processing fields. In this paper, we have implemented the lifting “Cohen-Daubechies-Feauveau 9/7” algorithm on a low cost NVIDIA's GPU (Graphics Processing Unit) with MatLab to achieve speedup in computation. The efficiency of our GPU based implementation is measured and compared with CPU based algorithms. Our investigational results with GPU show performance enhancement over a factor of 1.82 compared with CPU for an image of size 4096×4096 pixels.
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