Papers by Edmund Pierzchala
A circuit-topology-driven approach to Optical Proximity Correction (OPC) is presented. By tailori... more A circuit-topology-driven approach to Optical Proximity Correction (OPC) is presented. By tailoring device critical dimension (CD) statistical distribution to the device function in the circuit, and ensuring that the CD distribution stays within the correct (possibly variable) limits during process maturation and other process changes, it can be an effective tool for optimizing circuit's performance/yield tradeoff in high-volume manufacturing. Calibre's proprietary Programmable Electrical Rule Checks (PERC) module is used to recognize the topology. Alternatively, an external static timing tool can be used to identify critical devices.
The fitting problem for a new application-specific state machine device, CY7C361, from Cypress Se... more The fitting problem for a new application-specific state machine device, CY7C361, from Cypress Semiconductor is formulated, and a solution is proposed. This fitting problem consists of mapping the netlist obtained from high-level synthesis into the chip's physical resources. In general, the mapping (fitting) problem can be formulated as one of the labeled graph isomorphism between the netlist graph and the subgraph of the resources graph. However, the specific architecture-related constraints of the CY7C361 device cause the fitting problem to be generalized as a graph isomorphism problem with some additional mapping constraints. The formulation is quite general for a class of electronically programmable logic device (EPLD) fitting problems. An exact, constraint-based, tree searching algorithm with several kinds of backtracking was implemented
Current-mode amplifier/integrator for a field-programmable analog array
An electronically-programmable analog circuit (EPAC), based on the switched-capacitor (SC) techni... more An electronically-programmable analog circuit (EPAC), based on the switched-capacitor (SC) technique, is an analog counterpart of digital FPGAs. The full speed potential of analog circuits, however, can be utilized only by continuous-time (CT) field-programmable analog arrays (FPAAs). In this paper an example of an FPAA structure with local interconnections is shown. Each cell derives a weighted sum of selected signals from four nearest neighbors, and optionally performs integration (ideal or lossy) to produce its own output signal.
This paper presents a concept and an implementation of a current-mode integrator based on the Mil... more This paper presents a concept and an implementation of a current-mode integrator based on the Miller effect. The circuit has a highly lineal; no feedback, current path, implemented using a Gilbert amplifier cell, and a voltage feedback path with capacitors, realizing integration. A bipolar transistor array process with devices with an fT of 8 GHz has been used for the circuit simulation. Phase response of -90f0.5" has been obtained in the frequency range of 1 MHz to 670 MHz (the low-frequency pole can be tuned electronically down to about 3 Hz). Excess phase can be compensated electronically to obtain exactly -90" for any frequency in the entire useful range. The gain of the circuit can be tuned electronically over at least 40 dB.
Ternary and Quaternary Lattice Diagrams are introduced that can find applications to submicron de... more Ternary and Quaternary Lattice Diagrams are introduced that can find applications to submicron design, and designing new fine-grain digital, analog and mixed FPGAs. They expand the ideas of Lattice diagrams [6, 111 and Linearly Independent (LI) , 181. In a regular layout, every cell is connected to 4, 6 or 8 neighbors and to a number of vertical, horizontal and diagonal buses. Various lattices and algorithms for their creation are presented.
Analog Integrated Circuits and Signal Processing, 1998
This paper presents a variety of applications of an FPAA based on a regular pattern of signal-pro... more This paper presents a variety of applications of an FPAA based on a regular pattern of signal-processing cells and primarily local signal interconnections. Despite the limitations introduced by local interconnections, the presented architecture accommodates a wide variety of linear and nonlinear circuits found in many signal processing systems. Thus it effectively proves that it is possible to improve the performance of an FPAA by means of constraining the interconnection pattern, without significantly limiting the class of circuits it can implement.
The fitting problem for a new application-specific state machine device, CY7C361, from Cypress Se... more The fitting problem for a new application-specific state machine device, CY7C361, from Cypress Semiconductor is formulated, and a solution is proposed. This fitting problem consists of mapping the netlist obtained from high-level synthesis into the chip's physical resources. In general, the mapping (fitting) problem can be formulated as one of the labeled graph isomorphism between the netlist graph and the subgraph of the resources graph. However, the specific architecture-related constraints of the CY7C361 device cause the fitting problem to be generalized as a graph isomorphism problem with some additional mapping constraints. The formulation is quite general for a class of electronically programmable logic device (EPLD) fitting problems. An exact, constraint-based, tree searching algorithm with several kinds of backtracking was implemented
Knowledge based extension of DIADES system for the analysis and synthesis of TGC circuits
A new and uniform approach to the computer-aided analysis and synthesis of analog circuits is pre... more A new and uniform approach to the computer-aided analysis and synthesis of analog circuits is presented. The system is specialized for transconductance-grounded capacitance circuits (TGC). The analysis is a transformation from a signal flow graph (SFG) to a transfer function (TF). It is based on a step-by-step transformation from SFG to TF by reductions of nodes: summation, multiplication, and feedback. Symbol manipulation of multivariate rational functions is used. The synthesis is a process of transforming a LC-ladder filter SFG to a TGC circuit. Heuristic synthesis procedures, inverse to the ones used in the analysis, search the solution space of equivalent SFGs and are theoretically able to find the optimal solution. The synthesis method includes three stages: SFG labeling, synthesis of the SFG branch transfer functions, and SFG repolarization. The application of some synthesis rules is illustrated on examples
Current-mode amplifier/integrator for a field-programmable analog array
An electronically-programmable analog circuit (EPAC), based on the switched-capacitor (SC) techni... more An electronically-programmable analog circuit (EPAC), based on the switched-capacitor (SC) technique, is an analog counterpart of digital FPGAs. The full speed potential of analog circuits, however, can be utilized only by continuous-time (CT) field-programmable analog arrays (FPAAs). In this paper an example of an FPAA structure with local interconnections is shown. Each cell derives a weighted sum of selected signals from four nearest neighbors, and optionally performs integration (ideal or lossy) to produce its own output signal.
I n this paper we propose a novel approach to the realization of continuous, fiuzy, and multi-val... more I n this paper we propose a novel approach to the realization of continuous, fiuzy, and multi-valued logic (mvl) circuits.
This paper presents a concept and an implementation of a current-mode integrator based on the Mil... more This paper presents a concept and an implementation of a current-mode integrator based on the Miller effect. The circuit has a highly lineal; no feedback, current path, implemented using a Gilbert amplifier cell, and a voltage feedback path with capacitors, realizing integration. A bipolar transistor array process with devices with an fT of 8 GHz has been used for the circuit simulation. Phase response of -90f0.5" has been obtained in the frequency range of 1 MHz to 670 MHz (the low-frequency pole can be tuned electronically down to about 3 Hz). Excess phase can be compensated electronically to obtain exactly -90" for any frequency in the entire useful range. The gain of the circuit can be tuned electronically over at least 40 dB.
I n this paper we propose a novel approach to the realization of continuous, fiuzy, and multi-val... more I n this paper we propose a novel approach to the realization of continuous, fiuzy, and multi-valued logic (mvl) circuits.
Ternary and Quaternary Lattice Diagrams are introduced that can find applications to submicron de... more Ternary and Quaternary Lattice Diagrams are introduced that can find applications to submicron design, and designing new fine-grain digital, analog and mixed FPGAs. They expand the ideas of Lattice diagrams [6, 111 and Linearly Independent (LI) , 181. In a regular layout, every cell is connected to 4, 6 or 8 neighbors and to a number of vertical, horizontal and diagonal buses. Various lattices and algorithms for their creation are presented.
Analog Integrated Circuits and Signal Processing, 1998
This paper presents a variety of applications of an FPAA based on a regular pattern of signal-pro... more This paper presents a variety of applications of an FPAA based on a regular pattern of signal-processing cells and primarily local signal interconnections. Despite the limitations introduced by local interconnections, the presented architecture accommodates a wide variety of linear and nonlinear circuits found in many signal processing systems. Thus it effectively proves that it is possible to improve the performance of an FPAA by means of constraining the interconnection pattern, without significantly limiting the class of circuits it can implement.
We introduce a concept in VLSI layout which can nd applications in submicron design, quantum devi... more We introduce a concept in VLSI layout which can nd applications in submicron design, quantum devices, and designing new ne-grain FPGAs. This concept is called Lattice Structure and it extends the concepts from 8] and 1, . In the regular arrangement of cells, every cell is connected to 4, 6 or 8 neighbors and to vertical, horizontal and diagonal buses. Methods for expanding arbitrary binary and multi-valued combinational functions to this layout are illustrated.
Knowledge based extension of DIADES system for the analysis and synthesis of TGC circuits
A new and uniform approach to the computer-aided analysis and synthesis of analog circuits is pre... more A new and uniform approach to the computer-aided analysis and synthesis of analog circuits is presented. The system is specialized for transconductance-grounded capacitance circuits (TGC). The analysis is a transformation from a signal flow graph (SFG) to a transfer function (TF). It is based on a step-by-step transformation from SFG to TF by reductions of nodes: summation, multiplication, and feedback. Symbol manipulation of multivariate rational functions is used. The synthesis is a process of transforming a LC-ladder filter SFG to a TGC circuit. Heuristic synthesis procedures, inverse to the ones used in the analysis, search the solution space of equivalent SFGs and are theoretically able to find the optimal solution. The synthesis method includes three stages: SFG labeling, synthesis of the SFG branch transfer functions, and SFG repolarization. The application of some synthesis rules is illustrated on examples
Analog Integrated Circuits and Signal Processing, 1998
The design of a high-frequency field-programmable analog array (FPAA) is presented. The FPAA is b... more The design of a high-frequency field-programmable analog array (FPAA) is presented. The FPAA is based on a regular pattern of cells interconnected locally for high frequency performance. No switches of any kind are used in the signal path of a cell: programming of the functions, parameters, and interconnections is achieved solely by modifying cells' bias conditions digitally. Limited global signal interconnections are also available for those application circuits which cannot be mapped onto locally-only interconnected structure. Key circuits of the FPAA have been fabricated in a CPI transistor-array bipolar technology.
Ternary and quaternary lattice diagrams are introduced that can find applications to submicron de... more Ternary and quaternary lattice diagrams are introduced that can find applications to submicron design, and designing new fine-grain digital, analog and mixed FPGAs. They expand the ideas of lattice diagrams and linearly-independent (LI) logic. In a regular layout, every cell is connected to 4, 6 or 8 neighbors and to a number of vertical, horizontal and diagonal buses. Various lattices and algorithms for their creation are presented
I n this paper we propose a novel approach to the realization of continuous, fiuzy, and multi-val... more I n this paper we propose a novel approach to the realization of continuous, fiuzy, and multi-valued logic (mvl) circuits.
We propose a novel approach to the realization of continuous, fuzzy, and multi-valued logic (mvl)... more We propose a novel approach to the realization of continuous, fuzzy, and multi-valued logic (mvl) circuits. We demonstrate how a general-purpose field programmable analog array (FPAA), with cells realizing simple arithmetic operations on signals, can be used for this purpose. The FPAA, which is being implemented in a bipolar transistor array technology, operates from ±3.3 V or ±5 V power supplies and works in the range of frequencies up to several hundred MHz
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Papers by Edmund Pierzchala