Abstract: An embedded system consists of a set of heterogeneous components. These components may ... more Abstract: An embedded system consists of a set of heterogeneous components. These components may be software or hardware blocks with a limited specification. A global verification of such systems to check the equivalence between their implementation and ...
There is a growing need for e2e lightpaths for high volume data transferring applications such as... more There is a growing need for e2e lightpaths for high volume data transferring applications such as GridFTP and SAN. They wish to dynamically deploy lightpaths over multiple management domains. Research, sponsored by Canarie Inc., is underway to enable "customer-empowered networks" and to experiment them with the Canadian research network CA*Net4. New signaling and control approaches using Web Services have been proposed. One difficulty is that each domain must retain the control of their optical network infrastructure and ensure proper allocation of optical resources. Hence, it is important that the signaling takes into account the management constraints imposed by the different domains. This paper presents a policy-based approach for user-controlled lightpath provisioning. The work builds on the research around the new signaling approaches for realizing customer-empowered networks. We present an architecture based on Web Services allowing users or Grid applications to establish e2e lightpaths over multiple Autonomous Systems. To tackle the problem of admission control and to address the resource allocation issue, we developed policy restricted signaling which allows customers to reserve lightpaths over multiple domains while ensuring that management rules of each domain are enforced. The signaling has been implemented and the experiment on a small network composed of Cisco equipment proves the viability of our approach.
This paper presents an incremental method for automatic executable test case and test sequence ge... more This paper presents an incremental method for automatic executable test case and test sequence generation for a protocol modeled as communicating extended finite state machines (CEFSMs) with asynchronous communication. Instead of testing the protocol by computing the product of all CEFSMs, we test it by incrementally computing a partial product for each CEFSM C, taking into account only transitions which influence (or are influenced by) C, and generating test cases for it. The partial product for C represents the behavior of C when composed with parts of the other CEFSMs. Experimental results show that this method can be applied to systems of practical size. We also propose a method which reduces the size of the product machine for certain systems.
Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06), 2006
Multiprocessor system-on-chip is one of the main drivers of the semiconductor industry revolution... more Multiprocessor system-on-chip is one of the main drivers of the semiconductor industry revolution by enabling the integration of complex functionality on a single chip. Memory is becoming a key player for significant improvements in embedded systems (power, performance and area). With the emergence of more embedded multimedia applications in the industry, this issue becomes increasingly vital. These applications often use
Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06), 2006
... Bruno Girodias Université de Montréal [email protected] El Mostapha Aboulhamid Univer... more ... Bruno Girodias Université de Montréal [email protected] El Mostapha Aboulhamid Université de Montréal [email protected] Gabriela Nicolescu École Polytechnique de Montréal [email protected] ABSTRACT ...
This paper presents a method for automatic executable test case and test sequence generation whic... more This paper presents a method for automatic executable test case and test sequence generation which combines both control and data flow testing techniques. Compared to published methods, we use an early executability verification mechanism to reduce significantly the number of discarded paths. A heuristic which uses cycle analysis is used to handle the executability problem. This heuristic can be applied even in the presence of unbounded loops in the specification. Later, the generated paths are completed by postambles and their executability is re-verified. The final executable paths are evaluated symbolically and used for conformance testing purposes.
4th IEEE International Workshop on System-on-Chip for Real-Time Applications, 2004
The size of today's designs makes their validation very time consuming. To manage their c... more The size of today's designs makes their validation very time consuming. To manage their complexity, an evolution towards higher levels of abstraction is mandatory. This paper addresses the automatic validation of high-level requirements. It presents an approach to cope with their modeling and conceptual validation. This methodology relies on the use of a very high level formal language for modeling
... ca Youcef Bouchebaba, Pierre Paulin, Bruno Lavigueur ST Microelectronics {Youcef. ... An iter... more ... ca Youcef Bouchebaba, Pierre Paulin, Bruno Lavigueur ST Microelectronics {Youcef. ... An iteration j of loop nest Lk, is said to depend on an iteration i of loop nest Lk− 1, if i produces an element of array Ak− 1 which is used by j. The difference between these two vectors (ji) is ...
ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 1999
In this paper, we present a new method for verifying the realizability of a timing diagram with l... more In this paper, we present a new method for verifying the realizability of a timing diagram with linear timing constraints, thus ensuring that the implementation of the underlying interface is feasible. The method is based on the consistency of the timing constraints derived from the timing diagram and accepts unknown occurrence times for events produced by the environment.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143), 1998
We present a method for verifying the realizability of a timing diagram, ensuring the synthesis o... more We present a method for verifying the realizability of a timing diagram, ensuring the synthesis of the underlying interface is possible. If necessary, a heuristic is introduced to render explicit hidden timing constraints implied by the specification. A relative schedule of output events is computed, accepting input events from the complete timing space defined by the assumed constraints on the environment. Interface design is an important aspect of the design of digital microelectronic systems. This importance is growing with the complexity of digital circuits. In order to manage this complexity, hardware systems are designed as distributed systems which require well defined interactions between the different components. The communication protocol between components is characterized by temporal constraints, hence the proper timing of the interface controllers is crucial. Because of their simplicity, and expressiveness, timing diagrams (TDs) are used to specify the behavior of interfaces. Our work deals with the realizability of TD specifications, and the subsequent synthesis of interface controllers. Maximum separation , consistency[6], satisfiability[6], realizability and causality[1] are among the most important concepts developed in the literature on TDs with quantitative timing constraints. Maximum separation determines temporal distances between events in the TD, and it constitutes the basic computation on TDs that is used in other aspects of analysis. Consistency ensures that the given system of constraints has at least one solution. Compatibility verifies whether devices built according to their TD specifications can correctly interact when connected together. Authors of [1] define causality property as a sufficient condition of realizability and give a more elaborate solution to compatibility based on causality. In this work we present a new method for determining whether a TD is realizable. Our method can deal with concurrent constraints between input and output events not allowed in [1], and no causal partition over events is necessary, thus avoiding the complexity of determining causal partitions as in . The relative scheduling used in our method constitutes a generalization of relative scheduling, since the assume constraints can be bounded compared to unbounded only in [10]; we Also Address MREQ\
The present work addresses the problem of conformance testing for EFSM-based systems and especial... more The present work addresses the problem of conformance testing for EFSM-based systems and especially, the problem of automatically generating executable test cases. First, the most important description methods are presented. Then, the test generation methods for FSM (finite state machines)-based systems are described. However, since systems are more understood as extended finite state machines (EFSMs), existing test generation methods for
Design Technology for Heterogeneous Embedded Systems, 2012
Chapter 7 Wireless Design Platform Combining Simulation and Testbed Environments Alain Fourmigue,... more Chapter 7 Wireless Design Platform Combining Simulation and Testbed Environments Alain Fourmigue, Bruno Girodias, Luiza Gheorghe, Gabriela Nicolescu, and El ... PHY I/O. In modern architectures, the MAC layer usually interacts with a hardware device via a DMA controller. ...
ABSTRACT Consequences of transient faults represent a significant problem for today's ele... more ABSTRACT Consequences of transient faults represent a significant problem for today's electronic circuits and systems. As the probability of such errors increases, incorporation of error detection and correction mechanisms is mandatory. It is well known that traditional techniques that validate system's reliability do not cover the whole spectrum of fault scenarios, because fault models are linked to target architectures. Therefore, validating the completeness of robust fault tolerance techniques is a major issue when assessing reliability improvements these techniques can produce. In this paper, we propose an original approach to evaluate the system reliability with respect to Single Event Upset (SEU) errors. It is based on model-checking principles. In addition, a signature analysis technique is evaluated. This technique was previously validated using a simulation-based fault injection approach. Simulation results showed that no error escapes detection. However, simulation based fault injection cannot guarantee that all fault consequences have been investigated. This limitation motivates us to explore a formal verification approach that targets a complete validation. Model checking has a fundamental advantage over classic fault-injection techniques: it can cover all possible SEU fault scenarios from a predefined class. Results reported in this paper demonstrate the efficiency of this validation approach over usual simulation-based techniques.
This paper presents an approach for automatic executable test case and test sequence generation f... more This paper presents an approach for automatic executable test case and test sequence generation for a protocol modeled by an SDL system. Our methodology uses a unified method which tests an Extended Finite State Machine (EFSM) based system by using control and data flow techniques. To test an SDL system, it extracts an EFSM from each process then the system is tested by incrementally computing a partial product for each EFSM C, taking into account only transitions which influence (or are influenced by) C, and generating test cases for it. This process ends when the coverage achieved by the generated test cases is satisfactory or when the partial products for all EFSMs are tested. Experimental results show that this method can be applied to systems of practical size.
ACM Transactions on Design Automation of Electronic Systems, 2007
Multiprocessor system-on-a-chip (MPSoC) architectures have received a lot of attention in the pas... more Multiprocessor system-on-a-chip (MPSoC) architectures have received a lot of attention in the past years, but few advances in compilation techniques target these architectures. This is particularly true for the exploitation of data locality. Most of the compilation techniques for parallel ...
2006 49th IEEE International Midwest Symposium on Circuits and Systems, 2006
Anti-collision radars help prevent car accidents by detecting obstacles in front of vehicles equi... more Anti-collision radars help prevent car accidents by detecting obstacles in front of vehicles equipped with such systems. This task traditionally relies on a correlator, which searches for similarities between an emitted and a received wave. Other modules can then use the information produced by the correlator to compute the distance and the relative speed between the moving vehicle and the obstacle. We implemented such a system using FPGA. We used hardware blocks to implement the high demanding computing correlator and a soft-core processor to compute the distances and speeds. In order to improve the maximum detection distance reached by the correlation algorithm, we developed and tested a modified version of a Higher Order Statistics based algorithm. This work results in a detailed description of this new algorithm, its possible implementations and their FPGA synthesis results.
Proceedings 1988 IEEE International Conference on Computer Design: VLSI, 1988
A scheme for fault-tolerant triangular cellular interconnection networks is proposed. A fault mod... more A scheme for fault-tolerant triangular cellular interconnection networks is proposed. A fault model is defined which unifies the concept of usable and unusable faulty components. An algorithm for testing these networks with a minimal number of tests (8) is presented. This result is extended to other cellular networks. A constant number of tests independent of the network size (at most
Abstract: An embedded system consists of a set of heterogeneous components. These components may ... more Abstract: An embedded system consists of a set of heterogeneous components. These components may be software or hardware blocks with a limited specification. A global verification of such systems to check the equivalence between their implementation and ...
There is a growing need for e2e lightpaths for high volume data transferring applications such as... more There is a growing need for e2e lightpaths for high volume data transferring applications such as GridFTP and SAN. They wish to dynamically deploy lightpaths over multiple management domains. Research, sponsored by Canarie Inc., is underway to enable "customer-empowered networks" and to experiment them with the Canadian research network CA*Net4. New signaling and control approaches using Web Services have been proposed. One difficulty is that each domain must retain the control of their optical network infrastructure and ensure proper allocation of optical resources. Hence, it is important that the signaling takes into account the management constraints imposed by the different domains. This paper presents a policy-based approach for user-controlled lightpath provisioning. The work builds on the research around the new signaling approaches for realizing customer-empowered networks. We present an architecture based on Web Services allowing users or Grid applications to establish e2e lightpaths over multiple Autonomous Systems. To tackle the problem of admission control and to address the resource allocation issue, we developed policy restricted signaling which allows customers to reserve lightpaths over multiple domains while ensuring that management rules of each domain are enforced. The signaling has been implemented and the experiment on a small network composed of Cisco equipment proves the viability of our approach.
This paper presents an incremental method for automatic executable test case and test sequence ge... more This paper presents an incremental method for automatic executable test case and test sequence generation for a protocol modeled as communicating extended finite state machines (CEFSMs) with asynchronous communication. Instead of testing the protocol by computing the product of all CEFSMs, we test it by incrementally computing a partial product for each CEFSM C, taking into account only transitions which influence (or are influenced by) C, and generating test cases for it. The partial product for C represents the behavior of C when composed with parts of the other CEFSMs. Experimental results show that this method can be applied to systems of practical size. We also propose a method which reduces the size of the product machine for certain systems.
Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06), 2006
Multiprocessor system-on-chip is one of the main drivers of the semiconductor industry revolution... more Multiprocessor system-on-chip is one of the main drivers of the semiconductor industry revolution by enabling the integration of complex functionality on a single chip. Memory is becoming a key player for significant improvements in embedded systems (power, performance and area). With the emergence of more embedded multimedia applications in the industry, this issue becomes increasingly vital. These applications often use
Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06), 2006
... Bruno Girodias Université de Montréal [email protected] El Mostapha Aboulhamid Univer... more ... Bruno Girodias Université de Montréal [email protected] El Mostapha Aboulhamid Université de Montréal [email protected] Gabriela Nicolescu École Polytechnique de Montréal [email protected] ABSTRACT ...
This paper presents a method for automatic executable test case and test sequence generation whic... more This paper presents a method for automatic executable test case and test sequence generation which combines both control and data flow testing techniques. Compared to published methods, we use an early executability verification mechanism to reduce significantly the number of discarded paths. A heuristic which uses cycle analysis is used to handle the executability problem. This heuristic can be applied even in the presence of unbounded loops in the specification. Later, the generated paths are completed by postambles and their executability is re-verified. The final executable paths are evaluated symbolically and used for conformance testing purposes.
4th IEEE International Workshop on System-on-Chip for Real-Time Applications, 2004
The size of today's designs makes their validation very time consuming. To manage their c... more The size of today's designs makes their validation very time consuming. To manage their complexity, an evolution towards higher levels of abstraction is mandatory. This paper addresses the automatic validation of high-level requirements. It presents an approach to cope with their modeling and conceptual validation. This methodology relies on the use of a very high level formal language for modeling
... ca Youcef Bouchebaba, Pierre Paulin, Bruno Lavigueur ST Microelectronics {Youcef. ... An iter... more ... ca Youcef Bouchebaba, Pierre Paulin, Bruno Lavigueur ST Microelectronics {Youcef. ... An iteration j of loop nest Lk, is said to depend on an iteration i of loop nest Lk− 1, if i produces an element of array Ak− 1 which is used by j. The difference between these two vectors (ji) is ...
ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 1999
In this paper, we present a new method for verifying the realizability of a timing diagram with l... more In this paper, we present a new method for verifying the realizability of a timing diagram with linear timing constraints, thus ensuring that the implementation of the underlying interface is feasible. The method is based on the consistency of the timing constraints derived from the timing diagram and accepts unknown occurrence times for events produced by the environment.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143), 1998
We present a method for verifying the realizability of a timing diagram, ensuring the synthesis o... more We present a method for verifying the realizability of a timing diagram, ensuring the synthesis of the underlying interface is possible. If necessary, a heuristic is introduced to render explicit hidden timing constraints implied by the specification. A relative schedule of output events is computed, accepting input events from the complete timing space defined by the assumed constraints on the environment. Interface design is an important aspect of the design of digital microelectronic systems. This importance is growing with the complexity of digital circuits. In order to manage this complexity, hardware systems are designed as distributed systems which require well defined interactions between the different components. The communication protocol between components is characterized by temporal constraints, hence the proper timing of the interface controllers is crucial. Because of their simplicity, and expressiveness, timing diagrams (TDs) are used to specify the behavior of interfaces. Our work deals with the realizability of TD specifications, and the subsequent synthesis of interface controllers. Maximum separation , consistency[6], satisfiability[6], realizability and causality[1] are among the most important concepts developed in the literature on TDs with quantitative timing constraints. Maximum separation determines temporal distances between events in the TD, and it constitutes the basic computation on TDs that is used in other aspects of analysis. Consistency ensures that the given system of constraints has at least one solution. Compatibility verifies whether devices built according to their TD specifications can correctly interact when connected together. Authors of [1] define causality property as a sufficient condition of realizability and give a more elaborate solution to compatibility based on causality. In this work we present a new method for determining whether a TD is realizable. Our method can deal with concurrent constraints between input and output events not allowed in [1], and no causal partition over events is necessary, thus avoiding the complexity of determining causal partitions as in . The relative scheduling used in our method constitutes a generalization of relative scheduling, since the assume constraints can be bounded compared to unbounded only in [10]; we Also Address MREQ\
The present work addresses the problem of conformance testing for EFSM-based systems and especial... more The present work addresses the problem of conformance testing for EFSM-based systems and especially, the problem of automatically generating executable test cases. First, the most important description methods are presented. Then, the test generation methods for FSM (finite state machines)-based systems are described. However, since systems are more understood as extended finite state machines (EFSMs), existing test generation methods for
Design Technology for Heterogeneous Embedded Systems, 2012
Chapter 7 Wireless Design Platform Combining Simulation and Testbed Environments Alain Fourmigue,... more Chapter 7 Wireless Design Platform Combining Simulation and Testbed Environments Alain Fourmigue, Bruno Girodias, Luiza Gheorghe, Gabriela Nicolescu, and El ... PHY I/O. In modern architectures, the MAC layer usually interacts with a hardware device via a DMA controller. ...
ABSTRACT Consequences of transient faults represent a significant problem for today's ele... more ABSTRACT Consequences of transient faults represent a significant problem for today's electronic circuits and systems. As the probability of such errors increases, incorporation of error detection and correction mechanisms is mandatory. It is well known that traditional techniques that validate system's reliability do not cover the whole spectrum of fault scenarios, because fault models are linked to target architectures. Therefore, validating the completeness of robust fault tolerance techniques is a major issue when assessing reliability improvements these techniques can produce. In this paper, we propose an original approach to evaluate the system reliability with respect to Single Event Upset (SEU) errors. It is based on model-checking principles. In addition, a signature analysis technique is evaluated. This technique was previously validated using a simulation-based fault injection approach. Simulation results showed that no error escapes detection. However, simulation based fault injection cannot guarantee that all fault consequences have been investigated. This limitation motivates us to explore a formal verification approach that targets a complete validation. Model checking has a fundamental advantage over classic fault-injection techniques: it can cover all possible SEU fault scenarios from a predefined class. Results reported in this paper demonstrate the efficiency of this validation approach over usual simulation-based techniques.
This paper presents an approach for automatic executable test case and test sequence generation f... more This paper presents an approach for automatic executable test case and test sequence generation for a protocol modeled by an SDL system. Our methodology uses a unified method which tests an Extended Finite State Machine (EFSM) based system by using control and data flow techniques. To test an SDL system, it extracts an EFSM from each process then the system is tested by incrementally computing a partial product for each EFSM C, taking into account only transitions which influence (or are influenced by) C, and generating test cases for it. This process ends when the coverage achieved by the generated test cases is satisfactory or when the partial products for all EFSMs are tested. Experimental results show that this method can be applied to systems of practical size.
ACM Transactions on Design Automation of Electronic Systems, 2007
Multiprocessor system-on-a-chip (MPSoC) architectures have received a lot of attention in the pas... more Multiprocessor system-on-a-chip (MPSoC) architectures have received a lot of attention in the past years, but few advances in compilation techniques target these architectures. This is particularly true for the exploitation of data locality. Most of the compilation techniques for parallel ...
2006 49th IEEE International Midwest Symposium on Circuits and Systems, 2006
Anti-collision radars help prevent car accidents by detecting obstacles in front of vehicles equi... more Anti-collision radars help prevent car accidents by detecting obstacles in front of vehicles equipped with such systems. This task traditionally relies on a correlator, which searches for similarities between an emitted and a received wave. Other modules can then use the information produced by the correlator to compute the distance and the relative speed between the moving vehicle and the obstacle. We implemented such a system using FPGA. We used hardware blocks to implement the high demanding computing correlator and a soft-core processor to compute the distances and speeds. In order to improve the maximum detection distance reached by the correlation algorithm, we developed and tested a modified version of a Higher Order Statistics based algorithm. This work results in a detailed description of this new algorithm, its possible implementations and their FPGA synthesis results.
Proceedings 1988 IEEE International Conference on Computer Design: VLSI, 1988
A scheme for fault-tolerant triangular cellular interconnection networks is proposed. A fault mod... more A scheme for fault-tolerant triangular cellular interconnection networks is proposed. A fault model is defined which unifies the concept of usable and unusable faulty components. An algorithm for testing these networks with a minimal number of tests (8) is presented. This result is extended to other cellular networks. A constant number of tests independent of the network size (at most
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Papers by E. Aboulhamid