Dorothy Kucar

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Pedro Julian

Universidad Nacional del Sur

Thomas Britz

The University of New South Wales

Lafifa Jamal

University of Dhaka, Bangladesh

Mitchell Thornton

Southern Methodist University

Michael Morin

Université Laval

Dr. J. M. Ashfaque (MInstP)

Independent Researcher

ANNIE SELDEN

New Mexico State University

Fernando Sandoya Sánchez

ESPOL (Escuela Superior Politécnica del Litoral)

Angelamaria Cardone

University of Salerno

Walid Najjar

University of California, Riverside

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Papers by Dorothy Kucar

Interconnection modelling using distributed RLC models

The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings., 2003

In physical design software, it is often necessary to estimate net, i.e. interconnection delays. ... more In physical design software, it is often necessary to estimate net, i.e. interconnection delays. Interconnections are typically modelled as lumped RC circuits. This approximation is reasonable in technologies where overall delay is dominated by gate delays. With present sub 130 nm technologies, characteristic signal propagation lengths are comparable to signal wavelengths. Interconnections no longer allow currents to flow through efficiently,

Performance modeling for early analysis of multi-core systems

by Dorothy Kucar, Reinaldo Bergamaschi, Gi-Joon Nam, and Guoling Han

Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '07, 2007

Performance analysis of microprocessors is a critical step in defining the microarchitecture, pri... more Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems, including multiple cores, caches and busses, this problem is compounded by complex performance interactions between cores, caches and interconnections, as well as by tight interdependencies between performance, power and physical characteristics of the design (i.e., floorplan). Although there are many point tools for the analysis of performance, or power, or floorplan of complex systems-on-chip (SoCs), there are surprisingly few works on an integrated tool that is capable of analyzing these various system characteristics simultaneously and allow the user to explore different design configurations and their effect on performance, power, size and thermal aspects. This paper describes an integrated tool for early analysis of performance, power, physical and thermal characteristics of multi-core systems. It includes cycle-accurate, transaction-level SystemC-based performance models of POWER processors and system components (i.e., caches, buses). Power models, for power computation, physical models for floorplanning and packaging models for thermal analysis are also included. The tool allows the user to build different systems by selecting components from a library and connecting them together in a visual environment. Using these models, users can simulate and dynamically analyze the performance, power and thermal aspects of multi-core systems.

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Using Eigenvectors to Partition Circuits

by Dorothy Kucar and Anthony Vannelli

INFORMS Journal on Computing, 2006

them are represented as nets (edges that connect two or more vertices) in the form of a hypergrap... more them are represented as nets (edges that connect two or more vertices) in the form of a hypergraph. We seek a placement of vertices that groups like objects and separates unlike objects. This involves separating related objects into a few, possibly disjoint, blocks. These hypergraph-partitioning problems are NP-hard so cannot be solved exactly, except for very small instances. We develop

A novel eigenvector technique for Large Scale combinatorial problems in VLSI layout

by Anthony Vannelli and Dorothy Kucar

Journal of Combinatorial Optimization, 2002

Modern integrated circuit design involves laying out circuits which consist of millions of switch... more Modern integrated circuit design involves laying out circuits which consist of millions of switching elements or transistors. Due to the sheer complexity, optimizing the connectivity between transistors is a very difficult problem. How a circuit is interconnected is the single most important factor in performance criteria such as signal delay, power dissipation, circuit size and cost. These factors dictate that