IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1985
This paper discusses the algorithms and implementation necessary for computing time domain sensit... more This paper discusses the algorithms and implementation necessary for computing time domain sensitivities during circuit simulation. The adjoint approach and the direct approach have been studied, and it was concluded that the direct approach is the best for implementation. The direct approach allows the transient sensitivities to be computed concurrently in time with the normal simulation, and it has been demonstrated that accurate sensitivity computations can be obtained, by simply allowing the sensitivity circuits to use the same time steps as the original circuit. This implementation also incorporates the charge based model for the MOSFET's and those sensitivity derivations are shown. It has been found that the responses of the sensitivity circuits can be discontinuous, and that this is due to discontinuities in the derivatives of the charge with respect to voltage. Derivations for various performance function sensitivities in terms of the response sensitivities are also given.
To meet filter response specifications active filters usually must be tuned or adjusted, preferab... more To meet filter response specifications active filters usually must be tuned or adjusted, preferably by computer automation if the production level is high. In this paper, three generalized tuning algorithms which have appeared in recent literature are comparatively reviewed on the basis of their architecture, computational complexity, and effectiveness. Furthermore, a new method is presented for the tuning resistor and frequency selection problem, a problem relevant to all three methods. Two Monte Carlo simulation examples enhance the comparison and provide a demonstration.
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1983
The efficiency of several variance reduction techniques (in particular, importance sampling, stra... more The efficiency of several variance reduction techniques (in particular, importance sampling, stratified sampling, and control variates) are studied with respect to their application in estimating circuit yields. This study suggests that one essentially has to have a good approximation of the region of acceptability in order to achieve significant variance reduction. Further, all the methods considered are based, either explicitly or implicity, on the use of a model. The control variate method appears to be more practical for implementation in a general purpose statistical circuit analysis program. Stratified sampling is the most simple to implement, but yields only very modest reductions in the variance of the yield estimator. Lastly, importance sampling is very useful when there are few parameters and the yield is very high or very low; however, a good practical technique for its implementation, in general, has not been found.
In general, encoding for LDPC codes can be difficult to realize efficiently. The paper presents t... more In general, encoding for LDPC codes can be difficult to realize efficiently. The paper presents techniques and architectures for LDPC encoding that are efficient and practical for a particular class of codes. These codes are the irregular partitioned permutation LDPC codes recently introduced by the author (Hocevar, D.E., Proc. IEEE Int. Conf. on Commun., p.2708-12, 2003). Since these codes are quasi-cyclic, it is known that a simpler encoding process does exist. The paper goes beyond that basic method by exploiting other structural properties to allow for a simpler and faster encoding process, in both software and hardware. Solutions for some rank deficient codes are also given.
A reduced complexity decoder architecture via layered decoding of LDPC codes
We apply layered belief propagation decoding to our previously devised irregular partitioned perm... more We apply layered belief propagation decoding to our previously devised irregular partitioned permutation LDPC codes. These codes have a construction that easily accommodates a layered decoding and we show that the decoding performance is improved by a factor of two in the number of iterations required. We show how our previous flexible decoding architecture can be adapted to facilitate layered decoding. This results in a significant reduction in the number of memory bits and memory instances required, in the range of 45-50%. The faster decoding speed means the decoder logic can also be reduced by nearly 50% to achieve the same throughput and error performance. In total, the overall decoder architecture can be reduced by nearly 50%.
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1986
An integrated and efficient approach is developed for au tomated statistical circuit design. One ... more An integrated and efficient approach is developed for au tomated statistical circuit design. One major problem in statistical cir cuit design for MOS VLSI is the prohibitively expensive computational requirements. The objective is to find realistic, accurate, and efficient solutions for use in the MOS VLSI design area. An automated statistical characterization system has been developed to characterize a large number of MOS devices to obtain statistical information on device pa rameters. A statistical model for MOS VLSI circuits has been devel
Pattern-independent current estimation for reliability analysis of CMOS circuits
Accurate and efficient expected current is required in circuit designs to analyze electromigratio... more Accurate and efficient expected current is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drop, etc. A pattern-independent simulation approach for estimating this expected current waveform drawn by CMOS circuitry has been developed. Four original concepts are presented which allow an efficient and accurate estimation of expected current waveforms. They are: probability waveforms, probability waveform propagation, probabilistic circuit models, and statistical timing analysis. This approach is considerably faster than traditional methods and yields comparable results.>
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1991
Circuit simulation with SPICE or direct method simulators on a scalar processor is too costly and... more Circuit simulation with SPICE or direct method simulators on a scalar processor is too costly and time consuming to adequately support the design of VLSI circuits. However, the new high performance parallel processing systems offer an attractive alternative for improvement in computational throughput in order to satisfy circuit simulation requirements. A high degree of natural parallelism exists in the circuit simulation problem; potentially a large number of processors can be used efficiently. Three distinct approaches for obtaining parallel execution in direct method circuit simulators are investigated in this study. These approaches differ primarily in the size of the individual tasks used to obtain parallel execution. The relative advantages of each approach are examined and performance data from simulations on parallel processing systems are presented. For the third approach, very good parallel efficiency was obtained; in some cases, 99% parallelism has been observed.
OASYS: a tool for aiding in design of high performance linear circuits
A circuit-optimization tool, OASYS, and the way it has helped in the design of high-performance l... more A circuit-optimization tool, OASYS, and the way it has helped in the design of high-performance linear circuits is discussed. Performance requirements may be conflicting in nature; improving one performance may degrade another performance or the circuit may be so complex that it is impossible to analyze it to obtain correct device sizes. These problems are faced in the design of TLE2027/37 op amps, where the goal was to maximize the gain bandwidth of the op amps while keeping the phase margin within the desired constraint limits. Conventional techniques had failed to do this in a reasonable amount of time. The methodology in OASYS is to use sensitivities (with regard to design parameters) generated by SPICE2 and the mini-max algorithm to tune the design parameters to achieve the desired goal. OASYS was used to optimize the performance of the TL2027/37 op amps. The OASYS methodology is described with special emphasis on the algorithms used. Results for the TLE2027/37 op amps predicted by OASYS and those extracted from the lab are compared to prove the accuracy of this tool
A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder
Page 1. A FPGA and ASIC Implementation of Rate 1/2, 8088-b Irregular Low Density Parity Check Dec... more Page 1. A FPGA and ASIC Implementation of Rate 1/2, 8088-b Irregular Low Density Parity Check Decoder Yanni Chen and Dale Hocevar DSP Solutions R & D Center Texas Instruments Incorporated, Dallas, TX 75243. Email: {ynchen, hocevar}@ti.com ...
600 MHz DSP for baseband processing in 3G base stations
A 1.2 V 600 MHz 4800 MIPS DSP is a solution for baseband processing in 3G base stations. It is ba... more A 1.2 V 600 MHz 4800 MIPS DSP is a solution for baseband processing in 3G base stations. It is based upon a partitioning of the workload between a DSP core and two flexible forward error correction coprocessors. This allows the DSP to handle a larger number of channels and/or to incorporate advanced algorithms.
We develop a new construction criterion for BSPK space-time codes. Based on this criterion, we pr... more We develop a new construction criterion for BSPK space-time codes. Based on this criterion, we propose a new method of improving the performance of space-time codes, namely bit interleaving. Then, we provide a computationally effective, iterative way of decoding bit interleaved space-time codes. At the end, we note the 2 dB gain due to the new approach. A proposed 16 state bit interleaved code operates close to 3 dB from the outage probability
Starting with an ordinary parallel concatenated turbo encoder in a block fading Rayleigh channel,... more Starting with an ordinary parallel concatenated turbo encoder in a block fading Rayleigh channel, we introduce bit-interleaving of the outputs, not for time diversity, but to increase the coding gain. We develop a guideline metric for designing QPSK space-time codes which reveals both the coding and diversity advantage of the systems as well as showing that it is unnecessary to guarantee full space diversity to achieve good performance in Rayleigh fading. Using channel a priori information in the MAP iterations for decoding, we achieve frame error rates within 1 dB of the outage probability with only modest increases in decoding complexity.
In this paper, a reduced-complexity, scalable implementation of LDPC decoder is presented. The de... more In this paper, a reduced-complexity, scalable implementation of LDPC decoder is presented. The decoder architecture in this paper is an improved version of . The new architecture makes the implementation of multiple code rates, multiple block sizes and multiple standards LDPC decoder very straightforward. As an example, we implemented a parameterized decoder that supports the LDPC code in IEEE 802.16e standard, which requires code rates of 1/2, 2/3 and 3/4, with block sizes varying from 576 to 2304. The decoder is synthesized with Texas Instruments' 90 nm ASIC process technology, with a target operation frequency of 100 MHz, 15 decoding iterations, the maximum data rate is up to 256 Mbps.
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1985
This paper discusses the algorithms and implementation necessary for computing time domain sensit... more This paper discusses the algorithms and implementation necessary for computing time domain sensitivities during circuit simulation. The adjoint approach and the direct approach have been studied, and it was concluded that the direct approach is the best for implementation. The direct approach allows the transient sensitivities to be computed concurrently in time with the normal simulation, and it has been demonstrated that accurate sensitivity computations can be obtained, by simply allowing the sensitivity circuits to use the same time steps as the original circuit. This implementation also incorporates the charge based model for the MOSFET's and those sensitivity derivations are shown. It has been found that the responses of the sensitivity circuits can be discontinuous, and that this is due to discontinuities in the derivatives of the charge with respect to voltage. Derivations for various performance function sensitivities in terms of the response sensitivities are also given.
To meet filter response specifications active filters usually must be tuned or adjusted, preferab... more To meet filter response specifications active filters usually must be tuned or adjusted, preferably by computer automation if the production level is high. In this paper, three generalized tuning algorithms which have appeared in recent literature are comparatively reviewed on the basis of their architecture, computational complexity, and effectiveness. Furthermore, a new method is presented for the tuning resistor and frequency selection problem, a problem relevant to all three methods. Two Monte Carlo simulation examples enhance the comparison and provide a demonstration.
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1983
The efficiency of several variance reduction techniques (in particular, importance sampling, stra... more The efficiency of several variance reduction techniques (in particular, importance sampling, stratified sampling, and control variates) are studied with respect to their application in estimating circuit yields. This study suggests that one essentially has to have a good approximation of the region of acceptability in order to achieve significant variance reduction. Further, all the methods considered are based, either explicitly or implicity, on the use of a model. The control variate method appears to be more practical for implementation in a general purpose statistical circuit analysis program. Stratified sampling is the most simple to implement, but yields only very modest reductions in the variance of the yield estimator. Lastly, importance sampling is very useful when there are few parameters and the yield is very high or very low; however, a good practical technique for its implementation, in general, has not been found.
In general, encoding for LDPC codes can be difficult to realize efficiently. The paper presents t... more In general, encoding for LDPC codes can be difficult to realize efficiently. The paper presents techniques and architectures for LDPC encoding that are efficient and practical for a particular class of codes. These codes are the irregular partitioned permutation LDPC codes recently introduced by the author (Hocevar, D.E., Proc. IEEE Int. Conf. on Commun., p.2708-12, 2003). Since these codes are quasi-cyclic, it is known that a simpler encoding process does exist. The paper goes beyond that basic method by exploiting other structural properties to allow for a simpler and faster encoding process, in both software and hardware. Solutions for some rank deficient codes are also given.
A reduced complexity decoder architecture via layered decoding of LDPC codes
We apply layered belief propagation decoding to our previously devised irregular partitioned perm... more We apply layered belief propagation decoding to our previously devised irregular partitioned permutation LDPC codes. These codes have a construction that easily accommodates a layered decoding and we show that the decoding performance is improved by a factor of two in the number of iterations required. We show how our previous flexible decoding architecture can be adapted to facilitate layered decoding. This results in a significant reduction in the number of memory bits and memory instances required, in the range of 45-50%. The faster decoding speed means the decoder logic can also be reduced by nearly 50% to achieve the same throughput and error performance. In total, the overall decoder architecture can be reduced by nearly 50%.
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1986
An integrated and efficient approach is developed for au tomated statistical circuit design. One ... more An integrated and efficient approach is developed for au tomated statistical circuit design. One major problem in statistical cir cuit design for MOS VLSI is the prohibitively expensive computational requirements. The objective is to find realistic, accurate, and efficient solutions for use in the MOS VLSI design area. An automated statistical characterization system has been developed to characterize a large number of MOS devices to obtain statistical information on device pa rameters. A statistical model for MOS VLSI circuits has been devel
Pattern-independent current estimation for reliability analysis of CMOS circuits
Accurate and efficient expected current is required in circuit designs to analyze electromigratio... more Accurate and efficient expected current is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drop, etc. A pattern-independent simulation approach for estimating this expected current waveform drawn by CMOS circuitry has been developed. Four original concepts are presented which allow an efficient and accurate estimation of expected current waveforms. They are: probability waveforms, probability waveform propagation, probabilistic circuit models, and statistical timing analysis. This approach is considerably faster than traditional methods and yields comparable results.>
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1991
Circuit simulation with SPICE or direct method simulators on a scalar processor is too costly and... more Circuit simulation with SPICE or direct method simulators on a scalar processor is too costly and time consuming to adequately support the design of VLSI circuits. However, the new high performance parallel processing systems offer an attractive alternative for improvement in computational throughput in order to satisfy circuit simulation requirements. A high degree of natural parallelism exists in the circuit simulation problem; potentially a large number of processors can be used efficiently. Three distinct approaches for obtaining parallel execution in direct method circuit simulators are investigated in this study. These approaches differ primarily in the size of the individual tasks used to obtain parallel execution. The relative advantages of each approach are examined and performance data from simulations on parallel processing systems are presented. For the third approach, very good parallel efficiency was obtained; in some cases, 99% parallelism has been observed.
OASYS: a tool for aiding in design of high performance linear circuits
A circuit-optimization tool, OASYS, and the way it has helped in the design of high-performance l... more A circuit-optimization tool, OASYS, and the way it has helped in the design of high-performance linear circuits is discussed. Performance requirements may be conflicting in nature; improving one performance may degrade another performance or the circuit may be so complex that it is impossible to analyze it to obtain correct device sizes. These problems are faced in the design of TLE2027/37 op amps, where the goal was to maximize the gain bandwidth of the op amps while keeping the phase margin within the desired constraint limits. Conventional techniques had failed to do this in a reasonable amount of time. The methodology in OASYS is to use sensitivities (with regard to design parameters) generated by SPICE2 and the mini-max algorithm to tune the design parameters to achieve the desired goal. OASYS was used to optimize the performance of the TL2027/37 op amps. The OASYS methodology is described with special emphasis on the algorithms used. Results for the TLE2027/37 op amps predicted by OASYS and those extracted from the lab are compared to prove the accuracy of this tool
A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder
Page 1. A FPGA and ASIC Implementation of Rate 1/2, 8088-b Irregular Low Density Parity Check Dec... more Page 1. A FPGA and ASIC Implementation of Rate 1/2, 8088-b Irregular Low Density Parity Check Decoder Yanni Chen and Dale Hocevar DSP Solutions R & D Center Texas Instruments Incorporated, Dallas, TX 75243. Email: {ynchen, hocevar}@ti.com ...
600 MHz DSP for baseband processing in 3G base stations
A 1.2 V 600 MHz 4800 MIPS DSP is a solution for baseband processing in 3G base stations. It is ba... more A 1.2 V 600 MHz 4800 MIPS DSP is a solution for baseband processing in 3G base stations. It is based upon a partitioning of the workload between a DSP core and two flexible forward error correction coprocessors. This allows the DSP to handle a larger number of channels and/or to incorporate advanced algorithms.
We develop a new construction criterion for BSPK space-time codes. Based on this criterion, we pr... more We develop a new construction criterion for BSPK space-time codes. Based on this criterion, we propose a new method of improving the performance of space-time codes, namely bit interleaving. Then, we provide a computationally effective, iterative way of decoding bit interleaved space-time codes. At the end, we note the 2 dB gain due to the new approach. A proposed 16 state bit interleaved code operates close to 3 dB from the outage probability
Starting with an ordinary parallel concatenated turbo encoder in a block fading Rayleigh channel,... more Starting with an ordinary parallel concatenated turbo encoder in a block fading Rayleigh channel, we introduce bit-interleaving of the outputs, not for time diversity, but to increase the coding gain. We develop a guideline metric for designing QPSK space-time codes which reveals both the coding and diversity advantage of the systems as well as showing that it is unnecessary to guarantee full space diversity to achieve good performance in Rayleigh fading. Using channel a priori information in the MAP iterations for decoding, we achieve frame error rates within 1 dB of the outage probability with only modest increases in decoding complexity.
In this paper, a reduced-complexity, scalable implementation of LDPC decoder is presented. The de... more In this paper, a reduced-complexity, scalable implementation of LDPC decoder is presented. The decoder architecture in this paper is an improved version of . The new architecture makes the implementation of multiple code rates, multiple block sizes and multiple standards LDPC decoder very straightforward. As an example, we implemented a parameterized decoder that supports the LDPC code in IEEE 802.16e standard, which requires code rates of 1/2, 2/3 and 3/4, with block sizes varying from 576 to 2304. The decoder is synthesized with Texas Instruments' 90 nm ASIC process technology, with a target operation frequency of 100 MHz, 15 decoding iterations, the maximum data rate is up to 256 Mbps.
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Papers by Dale Hocevar