Munkang Choi

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Nicole Herbots

Arizona State University

PROF. OM PRAKASH SINHA

Amity University

Ernst Pernicka

Universität Heidelberg

Caroline J . Tully

University of Melbourne

Suseendran Jayachandran

IMEC

Sergio Granados

Clark University

Virginie Boucher

CSIC (Consejo Superior de Investigaciones Científicas-Spanish National Research Council)

Metalurgi Fisik (Physical Metallurgy) Reza Fadhila

State University of Medan

Osama El Hariri

Banha University At Egypt

Marc Walton

Northwestern University

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Papers by Munkang Choi

Effect of Process and Layout on Strain Enhancement from Dual Stress Liners

2006 16th Biennial University/Government/Industry Microelectronics Symposium, 2006

ABSTRACT Tensile and compressive stressed nitride liners have been used to increase the carrier m... more ABSTRACT Tensile and compressive stressed nitride liners have been used to increase the carrier mobility in n-channel and p-channel silicon transistors respectively. Simulations indicate how much of the stress in the film is transferred to the channel region and the magnitude of the stress in different directions. A simple bulk piezoresistive model was used to estimate the effect on carrier mobility. It is shown in the case of the n-channel transistors that the enhancement is due to the vertical stress component whereas in the case of p-channel devices the enhancement is due to the in-plane stresses. The effect of different process conditions such as film stress, thickness and method of deposition, on mobility enhancement, was also characterized. It is shown that the enhancement saturates with increasing nitride thickness but scales proportionally with the film stress. Detailed studies of the effect of the circuit layout on the final channel stress allow the critical layout parameters to be identified. The variation of device performance with the layout parameters is quantified and can be used to define design rules as well as equations to modify the device characteristics based on layout.

Analysis of microbump induced stress effects in 3D stacked IC technologies

2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International, 2012

ABSTRACT Besides the stress around Cu TSV&#39;s, also the stress induced by microbumps is a m... more ABSTRACT Besides the stress around Cu TSV&#39;s, also the stress induced by microbumps is a main contributor to transistor level stress. For complete and successful deployment of 3D IC all effects generating stress have to be addressed. Therefore, this work quantifies the stress and its effects associated with Cu microbumps and their interaction with underfill material in 3D stacks by using a combined experimental and theoretical approach. We report on the stress generated by backside microbumps affecting FETs through the thinned silicon die and the stress on the thin die caused by 3D stacking. We find that the FET current shifts reach over 40% due to the impact of stress. Additionaly, a FEM parametric study was performed to determine key stress reduction contributors in 3D stacks.

Material Engineering for 7nm FinFETs

(Invited) Material Engineering for 7nm FinFETs

ECS Transactions

Design rules and several candidate channel materials are explored for the 7nm technology node. Fi... more Design rules and several candidate channel materials are explored for the 7nm technology node. FinFET transistor architecture is chosen, and the analysis is performed using 3D modeling tools, including ballistic transport, Schrodinger-driven quantization, and band-to-band tunneling leakage. The comparative analysis of Si, SiGe, Ge, GaAs, InGaAs, and InAs channel materials points to InGaAs with more than 80% Ga content as the best candidate for low power applications at 7nm design rules.

Munkang Choi

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