Papers by Charles Sakamaki
A Digital Signal Processor Reducing Access Contention
Block normalization processor
Block normalization processor
Multiple-data bus architecture for a digital signal processor using variable-length instruction set with single instruction simultaneous control
Application specific integrated circuit (ASIC) for performing rapid speech compression in a mobile telephone system
A single chip QCELP vocoder for CDMA digital cellular
Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94
Emerging digital wireless communications systems designed for digital cellular, PCN, wireless loc... more Emerging digital wireless communications systems designed for digital cellular, PCN, wireless local loop, and satellite based portables are paving the way for global wireless communications. There is an increasing need for high performance, low cost, low power ...
A digital signal processor using a variable length instruction set
Reliability of a computer architecture may be increased through fault tolerance. However, fault t... more Reliability of a computer architecture may be increased through fault tolerance. However, fault tolerance is achieved at a price of decreased throughput. The Fault Tolerant Parallel Processor at the Charles Stark Draper Laboratory maintains high levels of reliability and throughput by combining technologies of fault tolerance and parallel processing. The architecture is based on a Network Element (NE), which performs the functions of fault tolerance and parallel processing. A design for two field programmable gate arrays (FPGAs) is proposed herein which will replace much of the NE and perform the communication, synchronization, and redundancy management functions within the NE. This will yield increased reliability, reduced size, and reduced power dissipation. These FPGAs will be integrated with the next implementation of the Fault Tolerant Parallel Processor. Thesis Supervisor: Title: Thomas F. Knight Associate Professor of Electrical Engineering Acknowledgments This work would not...
Cached memory system and cache controller for embedded digital signal processor
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Papers by Charles Sakamaki