Transmission Electron Microscopy Sample Preparation By Design-Based Recipe Writing in a DBFIB
Proceedings, Nov 1, 2018
Transmission electron microscopy (TEM) sample can be routinely made at a sub 30nm thickness and s... more Transmission electron microscopy (TEM) sample can be routinely made at a sub 30nm thickness and specific features in semiconductor device design are on the order of 30nm and smaller. As a result, small changes in pattern match registration can significantly influence the success or failure of proper TEM sample placement as an approximately 15nm shift in lamella placement can easily cause the sample to be off the feature of interest. To address this issue, design based recipe writing is being developed on a dual beam focused ion beam platform. The intent is to have the tool read a GDS file and pattern match the design information to physical wafer images in a similar fashion to state-of-the-art critical dimension scanning electron microscopy operation. While the results are very encouraging, more work needs to be done to ensure a TEM sample of approximately 30nm thickness is placed at the desired location.
CMP Defect Reduction and Mitigation: Practices and Future Trends
An exponential correlation is found to exist between the number of added defects on polished blan... more An exponential correlation is found to exist between the number of added defects on polished blanket wafers and the inverse of defect size for particulate CMP defects. Smaller surface defects are much more abundant and more difficult to remove. Pad surface pore geometry can influence the transport of debris during polish, and hence modulate the generation of defects such as polish residue (PR), foreign materials (FM), and scratches. The conditioner and conditioning process also plays a role. Besides the selection and optimization of cleaning chemical and post cleaning process itself, overall CMP defect reduction and mitigation must take into account the events and consumables in the polish modules. The drive towards finer and 3D device geometry presents further challenges in defect detection and reduction.
IEEE Transactions on Semiconductor Manufacturing, May 1, 2011
PWC (Process Window Centering) is an efficient methodology to validate or adjust and center the o... more PWC (Process Window Centering) is an efficient methodology to validate or adjust and center the overall process window for a particular lithography layer by detecting systematic and random defects. The PWC methodology incorporates a defect inspection and analysis of the entire die that can be automated to provide timely results. This makes it a good compromise between FEM (Focus Exposure Matrix), where centering is based only on CD (critical dimension) measurements of a few specific structures and PWQ (Process Window Qualification) which provides very detailed defect inspection and analysis, but is more time consuming for lithography centering. This paper describes the application of the PWC methodology for 22 nm lithography centering in IBM's Albany and East Fishkill development facilities using KLA-Tencor's 28xx brightfield defect inspection system.
Defectivity Characterization of post-CMP Voiding in 32nm Cu Metallization
ASMC ... proceedings, May 1, 2008
ABSTRACT The effects of various process parameters, including liner/seed deposition, electrodepos... more ABSTRACT The effects of various process parameters, including liner/seed deposition, electrodeposition process and chemistry, and CMP (chemical mechanical planarization), on the formation of void defects in 32 nm copper metallization was investigated using a KLA-Tencor brightfield defect detection system. Optimum process conditions were determined based on void defectivity levels.
Ring oscillators (ROs) are used for yield learning during the research phase of a CMOS technology... more Ring oscillators (ROs) are used for yield learning during the research phase of a CMOS technology generation. Based on electrical data and binning methods, we improve detection and classification fault methodologies and form a yield detractor pareto. Inline defect monitoring can help to estimate RO yield and is essential in CMOS technology research.
IEEE Transactions on Semiconductor Manufacturing, 2019
We detail the use of ring oscillators (ROs) for yield learning during the research phase of a CMO... more We detail the use of ring oscillators (ROs) for yield learning during the research phase of a CMOS technology generation. Failing circuits are located and classified based on electrical analysis of ROs and FETs (Field Effect Transistor) wired out from RO environments. Based on electrical data and binning methods, we improve detection and classification fault methodologies and form a yield detractor pareto. Inline defect monitoring can help to estimate RO yield and is essential in CMOS technology research.
In this paper, a case study on control of BEOL defectivity in a systematic way for the future AI ... more In this paper, a case study on control of BEOL defectivity in a systematic way for the future AI application is presented. A few novel methodologies were introduced to identify the source of defectivity in various BEOL sectors, such as, patterning, barrier deposition, plating, and CMP. We successfully reduced the defectivity to the level required to yield target AI devices.
An exponential correlation is found to exist between the number of added defects on polished blan... more An exponential correlation is found to exist between the number of added defects on polished blanket wafers and the inverse of defect size for particulate CMP defects. Smaller surface defects are much more abundant and more difficult to remove. Pad surface pore geometry can influence the transport of debris during polish, and hence modulate the generation of defects such as polish residue (PR), foreign materials (FM), and scratches. The conditioner and conditioning process also plays a role. Besides the selection and optimization of cleaning chemical and post cleaning process itself, overall CMP defect reduction and mitigation must take into account the events and consumables in the polish modules. The drive towards finer and 3D device geometry presents further challenges in defect detection and reduction.
Y-Shaped Carbon Nanotubes as Afm Probe for Analyzing Substrates with Angled Topography, Method for Their Manufacture, Method for Performing Atomic Force Microscopy and Method for Selectively Modifying the Surface of a Substrate Using Said Y-Shaped Nanotubes
Reticle defectivity was evaluated using two known approaches: direct reticle inspection and the i... more Reticle defectivity was evaluated using two known approaches: direct reticle inspection and the inspection of the wafer prints. The primary test vehicle was a reticle with a design consisting of 45 nm and 60 nm comb and serpentine structures in different orientations. The reticle was inspected in reflected light on the KLA 587 in a die-todie and a die-to-database mode. Wafers were exposed on a 0.25 NA full-field EUV exposure tool and inspected on a KLA 2800. Both methods delivered two populations of defects which were correlated to identify coinciding detections and mismatches. In addition, reticle defects were reviewed using scanning electron microscopy (SEM) to assess the printability. Furthermore, some images of the defects found on the 45 nm reticle used in the previous study were collected using actinic (EUV) microscopy. The results of the observed mask defects are presented and discussed together with a defect classification.
Transmission Electron Microscopy Sample Preparation By Design-Based Recipe Writing in a DBFIB
Proceedings, Nov 1, 2018
Transmission electron microscopy (TEM) sample can be routinely made at a sub 30nm thickness and s... more Transmission electron microscopy (TEM) sample can be routinely made at a sub 30nm thickness and specific features in semiconductor device design are on the order of 30nm and smaller. As a result, small changes in pattern match registration can significantly influence the success or failure of proper TEM sample placement as an approximately 15nm shift in lamella placement can easily cause the sample to be off the feature of interest. To address this issue, design based recipe writing is being developed on a dual beam focused ion beam platform. The intent is to have the tool read a GDS file and pattern match the design information to physical wafer images in a similar fashion to state-of-the-art critical dimension scanning electron microscopy operation. While the results are very encouraging, more work needs to be done to ensure a TEM sample of approximately 30nm thickness is placed at the desired location.
CMP Defect Reduction and Mitigation: Practices and Future Trends
An exponential correlation is found to exist between the number of added defects on polished blan... more An exponential correlation is found to exist between the number of added defects on polished blanket wafers and the inverse of defect size for particulate CMP defects. Smaller surface defects are much more abundant and more difficult to remove. Pad surface pore geometry can influence the transport of debris during polish, and hence modulate the generation of defects such as polish residue (PR), foreign materials (FM), and scratches. The conditioner and conditioning process also plays a role. Besides the selection and optimization of cleaning chemical and post cleaning process itself, overall CMP defect reduction and mitigation must take into account the events and consumables in the polish modules. The drive towards finer and 3D device geometry presents further challenges in defect detection and reduction.
IEEE Transactions on Semiconductor Manufacturing, May 1, 2011
PWC (Process Window Centering) is an efficient methodology to validate or adjust and center the o... more PWC (Process Window Centering) is an efficient methodology to validate or adjust and center the overall process window for a particular lithography layer by detecting systematic and random defects. The PWC methodology incorporates a defect inspection and analysis of the entire die that can be automated to provide timely results. This makes it a good compromise between FEM (Focus Exposure Matrix), where centering is based only on CD (critical dimension) measurements of a few specific structures and PWQ (Process Window Qualification) which provides very detailed defect inspection and analysis, but is more time consuming for lithography centering. This paper describes the application of the PWC methodology for 22 nm lithography centering in IBM's Albany and East Fishkill development facilities using KLA-Tencor's 28xx brightfield defect inspection system.
Defectivity Characterization of post-CMP Voiding in 32nm Cu Metallization
ASMC ... proceedings, May 1, 2008
ABSTRACT The effects of various process parameters, including liner/seed deposition, electrodepos... more ABSTRACT The effects of various process parameters, including liner/seed deposition, electrodeposition process and chemistry, and CMP (chemical mechanical planarization), on the formation of void defects in 32 nm copper metallization was investigated using a KLA-Tencor brightfield defect detection system. Optimum process conditions were determined based on void defectivity levels.
Ring oscillators (ROs) are used for yield learning during the research phase of a CMOS technology... more Ring oscillators (ROs) are used for yield learning during the research phase of a CMOS technology generation. Based on electrical data and binning methods, we improve detection and classification fault methodologies and form a yield detractor pareto. Inline defect monitoring can help to estimate RO yield and is essential in CMOS technology research.
IEEE Transactions on Semiconductor Manufacturing, 2019
We detail the use of ring oscillators (ROs) for yield learning during the research phase of a CMO... more We detail the use of ring oscillators (ROs) for yield learning during the research phase of a CMOS technology generation. Failing circuits are located and classified based on electrical analysis of ROs and FETs (Field Effect Transistor) wired out from RO environments. Based on electrical data and binning methods, we improve detection and classification fault methodologies and form a yield detractor pareto. Inline defect monitoring can help to estimate RO yield and is essential in CMOS technology research.
In this paper, a case study on control of BEOL defectivity in a systematic way for the future AI ... more In this paper, a case study on control of BEOL defectivity in a systematic way for the future AI application is presented. A few novel methodologies were introduced to identify the source of defectivity in various BEOL sectors, such as, patterning, barrier deposition, plating, and CMP. We successfully reduced the defectivity to the level required to yield target AI devices.
An exponential correlation is found to exist between the number of added defects on polished blan... more An exponential correlation is found to exist between the number of added defects on polished blanket wafers and the inverse of defect size for particulate CMP defects. Smaller surface defects are much more abundant and more difficult to remove. Pad surface pore geometry can influence the transport of debris during polish, and hence modulate the generation of defects such as polish residue (PR), foreign materials (FM), and scratches. The conditioner and conditioning process also plays a role. Besides the selection and optimization of cleaning chemical and post cleaning process itself, overall CMP defect reduction and mitigation must take into account the events and consumables in the polish modules. The drive towards finer and 3D device geometry presents further challenges in defect detection and reduction.
Y-Shaped Carbon Nanotubes as Afm Probe for Analyzing Substrates with Angled Topography, Method for Their Manufacture, Method for Performing Atomic Force Microscopy and Method for Selectively Modifying the Surface of a Substrate Using Said Y-Shaped Nanotubes
Reticle defectivity was evaluated using two known approaches: direct reticle inspection and the i... more Reticle defectivity was evaluated using two known approaches: direct reticle inspection and the inspection of the wafer prints. The primary test vehicle was a reticle with a design consisting of 45 nm and 60 nm comb and serpentine structures in different orientations. The reticle was inspected in reflected light on the KLA 587 in a die-todie and a die-to-database mode. Wafers were exposed on a 0.25 NA full-field EUV exposure tool and inspected on a KLA 2800. Both methods delivered two populations of defects which were correlated to identify coinciding detections and mismatches. In addition, reticle defects were reviewed using scanning electron microscopy (SEM) to assess the printability. Furthermore, some images of the defects found on the 45 nm reticle used in the previous study were collected using actinic (EUV) microscopy. The results of the observed mask defects are presented and discussed together with a defect classification.
Uploads
Papers by Carol Boye