Synthese portable pour micro-architectures a grain fin. Application aux turbo decodeurs et nanofabriques
TSI-Technique et …, 2006
RÉSUMÉ. Toutes les architectures reconfigurables se ressemblent. Pour faciliter leur intégration ... more RÉSUMÉ. Toutes les architectures reconfigurables se ressemblent. Pour faciliter leur intégration logicielle, l'atelier Madeo les représente dans un modèle commun utilisé par des outils de CAO génériques. L'implantation d'outils et langages de haut niveau s'appuie sur une couche ...
As CMOS technology approaches its physical limits several emerging technologies are investigated ... more As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation.
The problem of automatic circuit layout is a difficult problem since there is a huge number of de... more The problem of automatic circuit layout is a difficult problem since there is a huge number of devices and there are many physical constraints to be met. Nowadays with the aparition of nanoscale devices, the problem becomes even more complicated, due to the huge integration densities of such devices and to the high percentage of defects due to the bottom-up assembly process. In this context we propose an evolutive, generic CAD framework, able to compute circuit layouts for a large number of novel fabric architectures.
As CMOS technology approaches its physical limits several emerging technologies are investigated ... more As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design space exploration, with no compromise on device feasibility. This work presents a NASIC-compliant application-specific computing architecture template along with its performance models and optimization policies that support domain-space exploration. This architecture has up to 29X density advantage over CMOS, is completely compatible with the NASIC manufacturing pathway, and enables the creation of unique max-rate pipelined systems.
Regular 2D NASIC-based architecture and design space exploration
As CMOS technology approaches its physical limits several emerging technologies are investigated ... more As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design space exploration, with no compromise on device feasibility. This work presents a NASIC-compliant application-specific computing architecture template along with its performance models and optimization policies that support domain-space exploration. This architecture has up to 29X density advantage over CMOS, is completely compatible with the NASIC manufacturing pathway, and enables the creation of unique max-rate pipelined systems.
In turbo decoding of product codes, we propose an algorithm implementation, based on the Chase-Py... more In turbo decoding of product codes, we propose an algorithm implementation, based on the Chase-Pyndiah algorithm, which exhibits a modular, simple structure with fine grain parallelism. It is implemented into deep pipelined architectures, including an interleaving block decoding scheme, with good potential on FPGAs and MP-SoCs targets. We include an evaluation of the essential parameters of those architectures, which are situated in a different area of the block turbo decoder implementation design space 1 .
The design of CAD tools for nanofabrics involves new challenges not encountered with conventional... more The design of CAD tools for nanofabrics involves new challenges not encountered with conventional design flow used for CMOS technology. In this paper, we propose to define a new framework able to help the designer to map an application on a wide range of emerging nanofabrics. Our proposal is based on a variety of models that capture as well as isolate the differences between these fabrics. This tool supports the design flow starting from behavioral description up to final layout. It integrates fault-tolerant techniques and fabric-related density transformations with more conventional design automation techniques. After an overview of common requirements, physical models, and associated techniques, a case study in the context of NASIC fabrics is used to illustrate some of the concepts.
Synthese portable pour micro-architectures a grain fin. Application aux turbo decodeurs et nanofabriques
TSI-Technique et …, 2006
RÉSUMÉ. Toutes les architectures reconfigurables se ressemblent. Pour faciliter leur intégration ... more RÉSUMÉ. Toutes les architectures reconfigurables se ressemblent. Pour faciliter leur intégration logicielle, l'atelier Madeo les représente dans un modèle commun utilisé par des outils de CAO génériques. L'implantation d'outils et langages de haut niveau s'appuie sur une couche ...
As CMOS technology approaches its physical limits several emerging technologies are investigated ... more As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation.
The problem of automatic circuit layout is a difficult problem since there is a huge number of de... more The problem of automatic circuit layout is a difficult problem since there is a huge number of devices and there are many physical constraints to be met. Nowadays with the aparition of nanoscale devices, the problem becomes even more complicated, due to the huge integration densities of such devices and to the high percentage of defects due to the bottom-up assembly process. In this context we propose an evolutive, generic CAD framework, able to compute circuit layouts for a large number of novel fabric architectures.
As CMOS technology approaches its physical limits several emerging technologies are investigated ... more As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design space exploration, with no compromise on device feasibility. This work presents a NASIC-compliant application-specific computing architecture template along with its performance models and optimization policies that support domain-space exploration. This architecture has up to 29X density advantage over CMOS, is completely compatible with the NASIC manufacturing pathway, and enables the creation of unique max-rate pipelined systems.
Regular 2D NASIC-based architecture and design space exploration
As CMOS technology approaches its physical limits several emerging technologies are investigated ... more As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design space exploration, with no compromise on device feasibility. This work presents a NASIC-compliant application-specific computing architecture template along with its performance models and optimization policies that support domain-space exploration. This architecture has up to 29X density advantage over CMOS, is completely compatible with the NASIC manufacturing pathway, and enables the creation of unique max-rate pipelined systems.
In turbo decoding of product codes, we propose an algorithm implementation, based on the Chase-Py... more In turbo decoding of product codes, we propose an algorithm implementation, based on the Chase-Pyndiah algorithm, which exhibits a modular, simple structure with fine grain parallelism. It is implemented into deep pipelined architectures, including an interleaving block decoding scheme, with good potential on FPGAs and MP-SoCs targets. We include an evaluation of the essential parameters of those architectures, which are situated in a different area of the block turbo decoder implementation design space 1 .
The design of CAD tools for nanofabrics involves new challenges not encountered with conventional... more The design of CAD tools for nanofabrics involves new challenges not encountered with conventional design flow used for CMOS technology. In this paper, we propose to define a new framework able to help the designer to map an application on a wide range of emerging nanofabrics. Our proposal is based on a variety of models that capture as well as isolate the differences between these fabrics. This tool supports the design flow starting from behavioral description up to final layout. It integrates fault-tolerant techniques and fabric-related density transformations with more conventional design automation techniques. After an overview of common requirements, physical models, and associated techniques, a case study in the context of NASIC fabrics is used to illustrate some of the concepts.
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Papers by C. Dezan