Cyrus Bamji

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Vrije Universiteit Brussel

James Elkins

School of the Art Institute of Chicago

Maurizio Forte

Duke University

Paul Tobin

Dublin Institute of Technology

Fabio Cuzzolin

Oxford Brookes University

Roshan Chitrakar

Nepal College of Information Technology

Lev Manovich

Graduate Center of the City University of New York

Bogdan Gabrys

University of Technology Sydney

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Ataturk University

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Papers by Cyrus Bamji

7.6 A 512×424 CMOS 3D Time-of-Flight image sensor with multi-frequency photo-demodulation up to 130MHz and 2GS/s ADC

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014

ABSTRACT

A 0.13 μm CMOS System-on-Chip for a 512 × 424 Time-of-Flight Image Sensor With Multi-Frequency Photo-Demodulation up to 130 MHz and 2 GS/s ADC

IEEE Journal of Solid-State Circuits, 2015

We introduce a 512 × 424 time-of-flight (TOF) depth image sensor designed in a TSMC 0.13 μm LP 1P... more We introduce a 512 × 424 time-of-flight (TOF) depth image sensor designed in a TSMC 0.13 μm LP 1P5M CMOS process, suitable for use in Microsoft Kinect for XBOX ONE. The 10 μm × 10 μm pixel incorporates a TOF detector that operates using the quantum efficiency modulation (QEM) technique at high modulation frequencies of up to 130 MHz, achieves a modulation contrast of 67% at 50 MHz and a responsivity of 0.14 A/W at 860 nm. The TOF sensor includes a 2 GS/s 10 bit signal path, which is used for the high ADC bandwidth requirements of the system that requires many ADC conversions per frame. The chip also comprises a clock generation circuit featuring a programmable phase and frequency clock generator with 312.5-ps phase step resolution derived from a 1.6 GHz oscillator. An integrated shutter engine and a programmable digital micro-sequencer allows an extremely flexible multi-gain/multi-shutter and multi-frequency/multi-phase operation. All chip data is transferred using two 4-lane MIPI D-PHY interfaces with a total of 8 Gb/s input/output bandwidth. The reported experimental results demonstrate a wide depth range of operation (0.8-4.2 m), small accuracy error (1%), very low depth uncertainty (0.5% of actual distance), and very high dynamic range (64 dB). Index Terms-Natural user interface (NUI), time-of-flight (TOF), quantum efficiency modulation (QEM), range imaging, 3D imaging.

$Fig. 2. ToF multi frequency operation. (a) Low-frequency fp has no ambiguity but large depth uncertainty. (b) High-frequency f, has more ambiguity but small depth uncertainty. (c) Another high-frequency f. with small depth uncertainty. introduction of the operating principle of our TOF system. Then, we will explain the sensor chip architecture focusing on the main blocks from pixel design to readout engine. Finally, we will show experimental results from the sensor system. applications. The same components and techniques can be used in battery-operated devices with much lower power consump- tion because the area to be illuminated is far smaller resulting in a large depth range of 0.8 m to 3.5 m and re flectivity 0%—100% should be accommodated, and all objects t ower power in both the light source and chip due to very short integration times. The requirements for the 3-D system include several difficult to meet constraints, such as a wide field FOV) of 70° x 60°, anda small minimum detectable object size of 2 cm x 2 cm for detecting hand gestures at 3.5 m. M of view oreover, between hat meet the minimum object size and reflectivity criteria anywhere in the scene, even in the presence of 3 KIx of bright ind oor am- bient light, should be imaged within an uncertainty spec of 1% of the object distance (and 1.5% accuracy error). To avoid ex- cessive blurring, the data must be acquired in ess than 20 msec. Calibration time must be kept to a minimum, and accuracy and performance must be maintained over millions of parts and over relatively uncontrolled operating conditions. The operation principle of a TOF depth sensor is illustrated in Fig. 1. The signal amplitude transmitted by the optical source is represented as sin(wt), where w = 2a/f is the modulation fre- quency. The TOF required for this signal to traverse the distance z to the object, be reflected, and subsequently be detected by the TOF sensor introduces a phase shift y = 2zw/c, where c is the speed of light in air. The amplitude of the received signal (3 is a function of several factors, such as input light power and reflec- tivity of the object, however, the phase shift ~ depends only on the distance of the photodetector to the object and the refractive index of the medium where the imaging takes place. In this paper, we will present the detailed design of the 512 x 424 TOF system-on-chip (SoC) designed in a TSMC 0.13 um CMOS process, suitable for use in Microsoft Kinect for XBOX ONE that meets the indoor requirements explained above. In the following sections, we will start with a brief In our TOF chip, the clocks driving the optical detector and the optical source are modulated in synchrony. The received signal Gsin(wt — w) is mixed with a phase-delayed form of the signal driving the optical source sin(wt — oftset), which after low-pass filtering yields 0.58 cos(y — Wortset)-$

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Technology mapping for high-performance static CMOS and pass transistor logic designs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2001

Two new techniques for mapping circuits are p r oposed in this paper. The rst method, called the ... more Two new techniques for mapping circuits are p r oposed in this paper. The rst method, called the odd-level transistor replacement OTR method, has a goal that is similar to that of technology mapping, but without the restriction of a xed library size, and maps a circuit to a virtual library of complex static CMOS gates. The second technique, the Static CMOS PTL method, uses a mix of static CMOS and pass transistor logic PTL to realize the circuit, and utilizes the relation between PTL and binary decision diagrams. The methods are very e cient and can handle all of the ISCAS'85 benchmark circuits in minutes. A c omparison of the results with traditional technology mapping using SIS on di erent libraries shows an average delay reduction above 18 for OTR, and an average delay reduction above 35 for the Static CMOS PTL method, with signi cant savings in the area. 1 Introduction Technology mapping is a cornerstone of the logic synthesis process and this area has been well studied in the past. Most existing techniques for technology mapping are based on static pre-characterized libraries, and can be classi ed into four categories: rule-based mapping 13 , graph matching 15 , direct mapping 18 and functional mapping 20. However, with changes in device technologies and the use of more complex static CMOS gates for example, in silicon-on-insulator technology, where longer transistor stacks are permitted, the limitations of the library-based design are becoming apparent. A library of xed size restricts the design choices that are available to a circuit designer, while a dynamic library that is generated on the y enables a better exploration of the This work is supported in part by a Lucent T echnologies DAC graduate scholarship, by a gift from Intel Corporation, and by the NSF under contracts MIP-9502556 and MIP-9796305. 1 design space. This paper develops techniques for generating complex gates on the y and performing technology mapping for two t ypes of technologies: Static CMOS: A topological mapping method called the odd-level transistor replacement OTR is developed for library-less mapping to complex static CMOS gates. Mixed static CMOS pass transistor logic PTL: A Boolean functional mapping method using binary decision diagrams BDD's to map logic to PTL is developed. This paper employs a similar dynamic programming based framework for both of these problems, and although they are solved as separate problems, we present them together in one publication for this reason. 1.1 Library-less mapping Traditional methods for technology mapping are directed towards a speci c library and are targeted towards objectives such as minimizing the circuit delay, minimizing the area and reducing the power dissipation. Using a pre-characterized library methodology has the inherent disadvantage that the quality of the results is dependent on the richness of the library: a library with a larger number of cells is likely to lead to better results than a sparsely populated library. The impact of the library size on logic synthesis was shown in 14 , where it was demonstrated that using larger libraries can reduce the area usage as compared to using smaller libraries. However, a complicating factor is the e ect of deep-submicron technologies, where it has been shown 24 that the ratio of the delay of NAND NOR gates to the inverter delay is becoming smaller than in older technologies. This encourages the use of longer chains of pull-up pull-down logic in circuits, making the increased usage of complex gates in deep-submicron circuits more viable. While this leads to better circuit performance, it also complicates the problem of traditional library-based technology mapping. With the increasing use of complex gates in the design, the number of possible gate types increases exponentially 10. Therefore, the number of gates in any library of a reasonable size can only capture a small fraction of the total number of possibilities, and traditional technology mapping is too restrictive. To take full advantage of the availability o f complex gates, the idea of using a dynamic virtual library" is becoming attractive. In this approach, individual complex gates cells are generated on the y, instead of using a pre-characterized library. The translation of this new gate to a layout can be performed using a module generator.

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IMpixel 65nm BSI 320MHz demodulated TOF Image sensor with 3μm global shutter pixels and analog binning

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018

The quest for accurate, high-resolution, low-power-consumption, and small-footprint 3D depth came... more The quest for accurate, high-resolution, low-power-consumption, and small-footprint 3D depth cameras has driven a rapid improvement in Continuous-Wave (CW) Time-of-Flight (ToF) technology. Commercially available 3D image acquisition techniques include Stereo Vision, Structured Light, and ToF. CW ToF imaging systems offer excellent mechanical robustness, no baseline requirement, high effective depth image resolution, low computational cost, and simultaneous IR ambient light invariant intensity capture (Active Brightness). In a CW ToF camera, light from an amplitude modulated light source is backscattered by objects in the camera's field of view, and the phase delay of the amplitude envelope is measured between the emitted and reflected light. This phase difference is translated into a distance value for each pixel in the imaging array.

A Review of Indirect Time-of-Flight Technologies

IEEE Transactions on Electron Devices

Interleaving buffer insertion and transistor sizing into a single optimization

Buffer insertion is a technique that is used either to increase the driving power of a path in a ... more Buffer insertion is a technique that is used either to increase the driving power of a path in a circuit, or to isolate large capacitive loads that lie on noncritical or less critical paths. Gate sizing sets the sizes of gates within a circuit to achieve a given timing specification. Traditional design techniques perform gate sizing and buffer insertion as two separate and independent steps during synthesis. However, until sizing is performed, any information on capacitive loads is incomplete and therefore a buffer insertion algorithm must operate with incomplete information, leading to suboptimal results. Moreover, the insertion of buffers can change the structure of the circuit sufficiently so that it may lead to a different sizing solution from the unbuffered circuit. Therefore, these techniques of buffer insertion and sizing are intimately linked and it makes a lot of sense to integrate them into a single optimization. This work presents strategies to insert buffers in a circuit...

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Functional timing analysis for IP characterization

A method that characterizes the timing of Intellectual Property (IP) blocks while taking into acc... more A method that characterizes the timing of Intellectual Property (IP) blocks while taking into account IP functionality is presented. IP blocks are assumed to have multiple modes of operation specified by the user. For each mode, our method calculates IO path delays and timing constraints to generate a timing model. The method thus captures the mode-dependent variation in IP delays which, according to our experiments, can be as high as 90%. The special manner in which delay calculation is performed guarantees that IP delays are never underestimated. The resulting timing models are also compacted through a process whose accuracy is controlled by the user.

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An advanced timing characterization method using mode dependency

To address the problem of accurate timing characterization, this paper proposes a method that ful... more To address the problem of accurate timing characterization, this paper proposes a method that fully exploits mode dependency. It is based on the premise that circuit delays are determined largely by a set of control inputs for which the number of useful combinations, i.e., modes, is small for most practical circuits. We take the modedependent characterization approach further and enhance it so that the delays of the I/O paths between the control inputs and outputs are calculated more accurately. We prove that, with a careful choice of propagation conditions, our method can generate timing models with very tight path delays that are guaranteed to give correct results. Experimental results using real-life circuits show that circuit delays can vary significantly among different modes for both control and data input delays, and capturing this variation can have a significant impact on the overall system timing. 1.

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Transistor-level timing analysis using embedded simulation

IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140)

A high accuracy system for transistor-level static timing analysis is presented. Accurate static ... more A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accurately calculated. At the sub-micron level, calculating gate and interconnect delays using delay models can result in reduced accuracy. Instead, the proposed method calculates delays through numerical integration using an embedded circuit simulator. It takes into account short circuit current and carefully chooses the set of conditions that results in a tight upper bound of the worst case delay for each gate. Similar repeating transistor configurations of gates in the circuit are automatically identified and a novel interpolation based caching scheme quickly computes gate delays from the delays of similar gates. A tight object code level integration with a commercial high speed transistorlevel circuit simulator allows efficient invocation of the simulation.

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Modulation résonnante pour des caméras d'imagerie de faible portée et de faible puissance

Selon l'invention un dispositif d'imagerie de portee d'onde continue modulee en ampli... more Selon l'invention un dispositif d'imagerie de portee d'onde continue modulee en amplitude comporte un dispositif de signalisation configure pour emettre un signal d'illumination module en intensite. Un capteur d'image est configure pour acquerir une pluralite d'images d'une reflexion du signal d'illumination module. Les images acquises comportent des composants d'intensite et/ou de phase pour une pluralite de pixels du capteur d'image. Chaque pixel comprend une premiere borne de modulation ayant un premier composant capacitif. Un premier pilote est configure pour charger un premier ensemble de bornes de modulation de la pluralite de pixels. Un deuxieme pilote est configure pour charger un deuxieme ensemble de bornes de modulation de la pluralite de pixels. Un circuit de transfert de charge est connecte entre le premier ensemble de bornes de modulation et le deuxieme ensemble de bornes de modulation. Le circuit de transfert de charge est concu ...

Multiples sources optiques synchronisées pour systèmes de recherche de plage à temps de vol

La puissance optique d'un systeme a temps de vol est augmentee a l'aide d'une ou de p... more La puissance optique d'un systeme a temps de vol est augmentee a l'aide d'une ou de plusieurs unites d'emetteur optique auxiliaire qui peuvent etre sans fil (WOE), ou câblees au moyen d'une fiche (PWOE). Les unites WOE detectent la puissance optique emise par le systeme a temps de vol S out et emettent une puissance optique S out-n de preference synchronisee de facon dynamique en frequence et en phase par rapport a la puissance optique S out telle que recue par l'unite WOE. Chaque unite WOE inclut au moins un capteur optique permettant de detecter la puissance optique S out et une retroaction interne garantissant que la frequence et la phase de la puissance optique S out-n emise par l'unite WOE sont synchronisees de facon dynamique avec la frequence et la phase de la puissance optique S out emise par le systeme a temps de vol. Les unites PWOE n'ont pas besoin de retroaction interne mais sont calibrees par le systeme a temps de vol de maniere a faire c...

Procedes et dispositifs de gestion de la charge pour une detection tridimensionnelle en couleur

La presente invention concerne des structures et des procedes de lecture d'image en trois dim... more La presente invention concerne des structures et des procedes de lecture d'image en trois dimensions par modulation haute frequence incluant des structures de detecteur implantables sur CMOS utilisant le transfert de charge differentiel, y compris de detecteurs permettant un recueil de charge local horizontalement rapide et verticalement moins rapide. La reponse en longueur d'ondes de tels detecteurs peut se modifier dynamiquement en faisant varier les potentiels de grille. Les procedes pour la production de telles structures de detecteur sur des equipements conventionnels de fabrication de CMOS comportent une utilisation d'instructions 'riches' pour commander le processus de fabrication de facon a optimiser le detecteur d'image plutot que des circuits integres numeriques ou analogiques. L'une de ces structures de detecteur comporte des structures digitales longues ecartees qui recueillent rapidement la charge selon le sens d'ecartement, puis deplacen...

Capteur de distance, rouge, vert, bleu a puce unique (rvb-z)

L'invention concerne un capteur RVB-Z pouvant etre mis en oeuvre sur une puce a CI unique. Un... more L'invention concerne un capteur RVB-Z pouvant etre mis en oeuvre sur une puce a CI unique. Un diviseur de faisceau tel qu'un miroir chaud recoit et separe la premiere et la seconde energie optique de bande centrale entrante d'un objet cible, de preference, en composantes d'image RVB et en composantes NIR-Z. L'image RVB et les composantes Z sont detectees par les zones de reseau detecteurs de pixels RVB et NIR, qui produisent des donnees d'images respectives et des donnees Z. La taille de pixel et les resolutions de reseau de ces zones ne doivent pas etre egales, et les deux zones de reseau peuvent etre formees sur une puce a saillie commune. Un affichage utilisant les donnees d'image peut etre augmente des donnees Z afin d'aider a reconnaitre un objet cible. La structure obtenue combine une efficacite optique de faisceaux de division avec la simplicite d'une mise en oeuvre de puce a saillie unique. L'invention concerne egalement un procede uti...

Fast and Accurate Timing Characterization Using Functional Information

In deep submicrometer integrated circuit design, there is a growing need to quickly and accuratel... more In deep submicrometer integrated circuit design, there is a growing need to quickly and accurately characterize the timing of large circuit blocks. Accurate timing characterization requires making available as much timing information as possible at each step of the design process. Conventional fast characterization methods typically employ topological analysis, which can be inaccurate because of its inability to eliminate false paths. To address this problem, a new method for creating accurate timing models of circuit blocks by making efficient use of their functionality is introduced. The proposed mode-dependent characterization (ModeChar) method is based on calculating a distinct timing model for each mode of circuit operation and reflects the way practical circuits function. ModeChar produces a mode-dependent timing model that contains delay information for a given set of circuit modes. It is shown that circuit delays are never underestimated by the mode-dependent models. The con...

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Custom Silicon and Sensors Developed for a 2nd Generation Mixed Reality User Interface

2019 Symposium on VLSI Circuits

Microsoft Hololens 2, like its predecessor, is an untethered holographic mixed reality (MR) heads... more Microsoft Hololens 2, like its predecessor, is an untethered holographic mixed reality (MR) headset that transforms the way we communicate, create, and explore. Hololens 2 advances MR ergonomics, intuitive interactions, and immersion. We describe the custom sensors and compute silicon developed to give hands-free user control of the headset and applications. With 3D Time of Flight (TOF) depth sensing, eye tracking and spatial array microphones, working with low power compute blocks aggregated in a custom ASIC, the hardware enables a comfortable, low latency user interface that sets the user free to focus on their work. We conclude with a look at how these building blocks can enable further innovation in the Intelligent Edge.

Dispositif d'entree sensorielle portatif

L'invention concerne un dispositif d'entree (100) permettant d'inserer une entree dan... more L'invention concerne un dispositif d'entree (100) permettant d'inserer une entree dans un dispositif electronique portatif (101). Ce dispositif detecte le mouvement des doigts d'un utilisateur sur une surface de travail inerte, et transmet des signaux representant l'entree detectee au dispositif electronique. Ce dispositif d'entree peut prendre diverses formes, notamment un support (100A) ou un revetement de protection (100B) qui se fixe au dispositif electronique, ou une unite separee qui transmet des signaux au dispositif electronique par l'intermediaire d'une connexion sans fil. Dans un mode de realisation de cette invention, des techniques sont utilisees pour placer correctement le dispositif d'entree independamment du reglage de l'utilisateur par rapport a la position de ce dispositif electronique (101). Dans un autre mode de realisation de cette invention, d'autres techniques sont utilisees pour maximiser la stabilite du dispositif d...

Global Shutter Pixel Structures with Shared Transfer Gates

The systematic exploration of pipelined array multiplier performance

ICASSP '85. IEEE International Conference on Acoustics, Speech, and Signal Processing

... PERFORMANCE Charles E. Hauck, Cyrus S. Bamji, and Jonathan Allen ... 38.3.1 nsefnl for VLSI o... more

Burst-Mode Time-Of-Flight Imaging

In a computer automated design system

7.6 A 512×424 CMOS 3D Time-of-Flight image sensor with multi-frequency photo-demodulation up to 130MHz and 2GS/s ADC

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014

ABSTRACT

A 0.13 μm CMOS System-on-Chip for a 512 × 424 Time-of-Flight Image Sensor With Multi-Frequency Photo-Demodulation up to 130 MHz and 2 GS/s ADC

IEEE Journal of Solid-State Circuits, 2015

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Technology mapping for high-performance static CMOS and pass transistor logic designs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2001

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IMpixel 65nm BSI 320MHz demodulated TOF Image sensor with 3μm global shutter pixels and analog binning

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018

A Review of Indirect Time-of-Flight Technologies

IEEE Transactions on Electron Devices

Interleaving buffer insertion and transistor sizing into a single optimization

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Functional timing analysis for IP characterization

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An advanced timing characterization method using mode dependency

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Transistor-level timing analysis using embedded simulation

IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140)

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Modulation résonnante pour des caméras d'imagerie de faible portée et de faible puissance

Multiples sources optiques synchronisées pour systèmes de recherche de plage à temps de vol

Procedes et dispositifs de gestion de la charge pour une detection tridimensionnelle en couleur

Capteur de distance, rouge, vert, bleu a puce unique (rvb-z)

Fast and Accurate Timing Characterization Using Functional Information

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Custom Silicon and Sensors Developed for a 2nd Generation Mixed Reality User Interface

2019 Symposium on VLSI Circuits

Dispositif d'entree sensorielle portatif

Global Shutter Pixel Structures with Shared Transfer Gates

The systematic exploration of pipelined array multiplier performance

ICASSP '85. IEEE International Conference on Acoustics, Speech, and Signal Processing

... PERFORMANCE Charles E. Hauck, Cyrus S. Bamji, and Jonathan Allen ... 38.3.1 nsefnl for VLSI o... more

Burst-Mode Time-Of-Flight Imaging

In a computer automated design system

Cyrus Bamji

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