2019 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI), 2019
Power Distribution Network (PDN) design is an important part of high-speed digital designs. In or... more Power Distribution Network (PDN) design is an important part of high-speed digital designs. In order to meet the need of high operation speed and low power voltage supply, the impedance of PDN should be lower than the target impedance of the design requirement. Decoupling capacitors are added on the PCB to lower the PDN impedance. The PCB PDN design is often guided by design rules and experience. In this paper, commonly-used PCB PDN designs are analyzed and categorized based on inductance contribution from specific portions of the current path. Then, the inductance components are quantified for different parts of the geometry in different designs.
An approach is presented for power integrity analysis on multi-layer printed circuit boards in th... more An approach is presented for power integrity analysis on multi-layer printed circuit boards in this paper. Two critical current paths are analyzed. Inductance decomposition is applied to identify the critical parameters that can influence the PDN input impedance. Two types of stack-ups are used to perform sensitivity analysis to illustrate the effectiveness of PDN design guidelines. Based on the analysis of the inductance contribution from different blocks in the PCB PDN, a systematic approach to obtain a complete understanding of PDN behavior is proposed. The approach can be used to provide design guidance in PDN design practice.
2017 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI), 2017
Statistical link analysis and link budget calculation is the essential part for current high-spee... more Statistical link analysis and link budget calculation is the essential part for current high-speed system design. Because of the difficulty of low bit-error rate (BER) simulation at SPICE transient solver, several methods were proposed to simulate low BER in a short time. Single-bit response (SBR) method is the most basic method; it uses SBR to construct the arbitrary waveform under the assumption of linear and time-invariant (LTI) system. However it cannot be applied to real system because I/O drivers are nonlinear. There exists a method to include these nonlinearity of real system, which is called as multiple-edge response (MER) method. There's a few paper to explain MER method, but no paper covers statistical analysis for the real system including ISI, x-talk, and power noise. In this paper, we demonstrate MER method for simple, but real HBM channel and also shows calculation burden of MER as the number of channels increase or MER order increases. Additionally, simple concept is proposed to apply MER on real HBM channel with more than a thousand I/Os.
2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI), 2018
The paper applies the combined SI-PI co-simulation to on chip high speed interconnects. A complet... more The paper applies the combined SI-PI co-simulation to on chip high speed interconnects. A complete model of chip and interposer PDN is developed and, together to a lumped model of the PCB and package PDN, it is employed to supply I/O drivers for HBM traces laid out on silicon interposer. A comprehensive analysis is carried out highlighting the impact of the decoupling capacitor placement and their corresponding parasitic inductance on the supply voltage ripple and on the output eye diagram at the signal receivers.
Application of the Thru-Reflect-Line (TRL) calibration to time domain measurements of S-parameter... more Application of the Thru-Reflect-Line (TRL) calibration to time domain measurements of S-parameters (t-TRL) allows for significantly increasing an accuracy of the obtained results. However, the accuracy of the t-TRL is still lower than that of the frequency domain vector network analyzers (VNA). There are two main sources of inaccuracies in the t-TRL calibration: random errors, such as an additive noise and jitter, and systematic errors associated with cables, connectors, and port mismatches. The paper addresses these two types of errors by proper selection of the number of sampling points, waveform averages, and record time. The PCB dielectric parameters extraction tool based on TDR/TDT measurements together with the t-TRL calibration has been developed
The injector of the European XFEL was initially designed for the operation with 1nC bunch charges... more The injector of the European XFEL was initially designed for the operation with 1nC bunch charges [1]. Later the flexibility of the nominal design of the injector with respect to the bunch charge was studied and extended also for smaller bunch charges down to 20pC [2]. A very tempting upgrade of this extension would be the operation of the European XFEL with different charges in the same train. It would make it suitable also for the experiments which require simultaneously different SASE pulse length or radiation power. In this paper we have investigated the possibility of the operation of different charges in the bunch train for the nominal design of the injector and for the case that it is extended by an additional laser system on the cathode. We have examined the problem of similarity of beam optical functions for different bunches in a train. We report also about the sensitivity of the beam optical functions on the chosen compression scenario and give an overview over the working points for the settings at the injector for single charge operation as well as combined working points for different bunch pairs.
Presented herein is an integrated test apparatus that may be used to test both Light Emitting Dio... more Presented herein is an integrated test apparatus that may be used to test both Light Emitting Diode (LED) and transceiver port features of a network device. DETAILED DESCRIPTION Many network devices, such as switches and routers, are configured to use LEDs to indicate the current status of certain device features, such as port status. These LEDs indicating the status of device features are sometimes referred to as “Status LEDs” (e.g., Port Status LED shows the current port status). These features are 100% tested during the production process, but require a set of standalone LED test stations. There are several issues with this step. In particular, network devices tend to have many ports to support different optical/Copper modules (e.g., SFP+, QSFP, and QSFP-DD) and the Status LEDs for each of these ports need to be 100% tested. In addition, the test time per network device is long and often inaccurate. The conventional testing techniques require separate test steps in the process th...
IEEE Transactions on Electromagnetic Compatibility, 2019
An evaluation is presented on the <italic>L</italic>–2<italic>L</italic> ... more An evaluation is presented on the <italic>L</italic>–2<italic>L</italic> de-embedding method for on-chip transmission lines. The method is analyzed using measurement data from two chips. Results are presented in terms of scattering parameters, as is the standard for characterizing system interconnects. The various challenges associated with on-chip modeling and measurements are discussed. Furthermore, a revised version of the <italic>L</italic>–2 <italic>L</italic> method is presented, decreasing its sensitivity to measurement noise. All de-embedding results are compared back to “ideal” simulation models for validation or disproof.
IEEE Transactions on Electromagnetic Compatibility, 2017
In this paper, a novel de-embedding methodology is proposed for through silicon via (TSV) charact... more In this paper, a novel de-embedding methodology is proposed for through silicon via (TSV) characterization by using a set of simple yet efficient test patterns. For all the test patterns, full wave models are developed and the electrical performance of the test patterns is analyzed thoroughly. Furthermore, broadband measurements are performed for the test patterns to verify the accuracy of the developed full wave models up to 40 GHz. Correlation between measurement and simulation results is discussed after optimizing the full wave models based on scanning electron microscope measurement. Analysis of measurement error is available as well. The proposed de-embedding method is applied to both the simulation and measurement results to extract the electrical characteristics of the TSV pair. Good agreement between the de-embedded results with analytical solution and the full-wave simulation for a standalone TSV pair indicates that the proposed de-embedding method works effectively up to 40 GHz. Finally, sensitivity analysis with regard to manufacturing tolerance of the test patterns to the final de-embedded results is performed.
IEEE Transactions on Instrumentation and Measurement, 2017
Novel de-embedding launch geometries and a simplified analytical procedure are proposed to extrac... more Novel de-embedding launch geometries and a simplified analytical procedure are proposed to extract the exact electromagnetic behavior of a through silicon via (TSV) pair from measured data. First, the most recent de-embedding method is reviewed and it is deeply investigated using both 3-D simulation and vector network analyzer measurements to accurately evaluate its residual error. Then, some potential sources of error are hypothesized and overcome by the proposed launch geometries based on a de-embedding plane that is able to ensure a TEM (or quasi-TEM) mode propagation. The novel launches are studied through 3-D simulations; the previous de-embedding procedure is updated to consider the fringing effect of the open-end launch, and it is simplified reducing the launch standards from three to two. The proposed launch geometries and algorithm are shown to be more accurate in the TSV pair de-embedding with respect to the method currently employed. Index Terms-De-embedding, fringing effect, through silicon vias (TSVs), vector network analyzer (VNA) measurements. I. INTRODUCTION T HROUGH silicon vias (TSVs) represent an essential element in the current 3-D integrated circuit (IC) technology for overcoming the limits of the traditional 2-D system in package in terms of bandwidth, size, and power consumption. The main advantage is that TSVs allow to stack multiple ICs while maintaining the same surface, thus minimizing the interconnect length and thus the power losses [1]-[3]. This current trend in the electronics miniaturization requires the continuous development of more sophisticated measurement techniques for testing the ICs and devices [4]-[6],
2016 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC), 2016
A transient simulation analysis is proposed for printed circuit board (PCB) power distribution ne... more A transient simulation analysis is proposed for printed circuit board (PCB) power distribution network (PDN) by using physics based circuit model. The PCB PDN is divided into different blocks. Different modeling methods are used to provide physics-based circuit models for each block. Then, Hspice simulation is used to do transient simulation for the PCB PDN based on the circuit.
2016 IEEE International Symposium on Electromagnetic Compatibility (EMC), 2016
A decomposition method for the PCB PDN voltage ripple caused by the IC switching current is devel... more A decomposition method for the PCB PDN voltage ripple caused by the IC switching current is developed based on an equivalent circuit model from a cavity model. The decomposition is presented both in frequency domain and time domain. Along with this decomposition approach, a one-to-one correspondence between the voltage ripple and the geometry is revealed. Guidelines to decrease the PCB PDN voltage ripple is also discussed and corroborated by both simulation and analytical calculation.
2016 IEEE International Symposium on Electromagnetic Compatibility (EMC), 2016
In this paper, the electrical performance of the test patterns used in the de-embedding method fo... more In this paper, the electrical performance of the test patterns used in the de-embedding method for TSV characterization was studied thoroughly. For all test patterns, full wave models were built and then analyzed based on simulated electrical performances. Equivalent circuit model analysis and parametric study results of the test patterns further demonstrate the accuracy of the full wave models. Furthermore, Scanning Electron Microscopy (SEM) measurements were taken for all the test patterns, and full wave models were optimized based on the measured dimensions. Finally, the response of the TSV pair was obtained by de-embedding the pads and traces from the TSV pair simulation with the test fixtures. Good agreement between the de-embedded results with analytical characterization and the full-wave simulation for a single TSV pair was achieved.
2016 IEEE 20th Workshop on Signal and Power Integrity (SPI), 2016
In this work the circuit segmentation approach for the modeling of Through Silicon Vias (TSV) is ... more In this work the circuit segmentation approach for the modeling of Through Silicon Vias (TSV) is extended to the presence of time domain non linear phenomena such as depletion and capacitance hysteresis. Results are shown discussing the impact of the voltage bias on the above mentioned non-linear phenomena and their combined impact on crosstalk among TSV and between TSVs and active circuits.
2015 Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC), 2015
This paper looksat the impact of consideringthe exact or approximated values for the nonlinear de... more This paper looksat the impact of consideringthe exact or approximated values for the nonlinear depletion capacitance in a TSV equivalent circuit for transient analysis. Furthermore, the effects of the time variant and nonlinear behavior of the doped bulk silicon substrate on signal propagation and crosstalk are also studied.
2015 IEEE Symposium on Electromagnetic Compatibility and Signal Integrity, 2015
Printed circuit board (PCB) power distribution network (PDN) design performance depends on the pe... more Printed circuit board (PCB) power distribution network (PDN) design performance depends on the peak voltage ripple caused by the integrated circuit (IC) switching currents. The input impedance seen by the IC looking into the PCB PDN can be calculated using a physics-based circuit model extracted from the cavity model approach. The input impedance is fitted to a simplified circuit model used to represent the PCB PDN. Using a switching current profile, the frequency domain noise voltage is found and transformed to the time domain ripple waveform which can then be used to evaluate the PDN design performance.
2009 IEEE International Symposium on Electromagnetic Compatibility, 2009
Characterizing materials used in Printed Circuit Board (PCB) manufacturing is becoming increasing... more Characterizing materials used in Printed Circuit Board (PCB) manufacturing is becoming increasingly important in link path analysis as the data rates are increasing. The material properties governing the performance of the signal passing through a transmission line are frequency-dependent. Using frequency-domain vector network analyzer (VNA) measurements and Through-Reflect-Line (TRL) calibration, these parameters can be determined accurately. But a Time-Domain Reflectometer (TDR) provides a relatively inexpensive and simple way of characterizing transmission lines, and it is easily accessible to Signal Integrity engineers. With the timedomain TRL (t-TRL) calibration technique [1], it is now possible to de-embed such discontinuities as connectors, cables, etc., in the path of the transmission line using time-domain measurements. From the calibrated results, material properties can be extracted in the same way as it is done in the frequency domain. This paper describes a t-TRL technique to obtain accurate frequency domain S-parameters from time domain measurements. The calibrated results are converted into the ABCD parameters. The propagation constant is obtained through the ABCD parameters, from which attenuation loss and phase constant are extracted. Dielectric constant is extracted from the phase constant and the total attenuation constant. Curve-fitting technique is used to split the losses into conductor and dielectric loss. Once dielectric loss is determined, loss tangent can be calculated. The results are compared for three test vehicles, and are also compared with frequency domain VNA measurements. The results from the t-TRL calibration technique are also compared with another known extraction procedure.
A modeling methodology to calculate the decoupling capacitor interconnect inductance in a multi-l... more A modeling methodology to calculate the decoupling capacitor interconnect inductance in a multi-layer PCB is proposed herein. The methodology is based on the resonant cavity model of parallel planes. The self-inductance and mutual inductance are extracted to understand the via configuration influence on the effectiveness of decoupling capacitors. A special layout of decoupling capacitor is proposed to increase the effectiveness of the decoupling capacitors by taking maximum advantage of the mutual inductance between interconnect vias with two decoupling capacitors placed in a pair, and two pairs of power and ground vias placed in alternating directions as close as possible. The number of decoupling capacitors needed can be reduced dramatically. Three PCB PDN designs are used to present the effectiveness of doublet layout in different design scenarios. Similar analysis is extended to 3-terminal decoupling capacitor layout design. The decoupling capacitor interconnect inductance of the five via layouts for 3-terminal capacitors is analyzed. The number of decoupling capacitors needed for a commercial product using the doublet layout and 3-terminal capacitor layout is compared to the design with an alternating decoupling capacitor layout to reflect the impact of the decap layout design on the PCB PDN performance.
2019 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI), 2019
Power Distribution Network (PDN) design is an important part of high-speed digital designs. In or... more Power Distribution Network (PDN) design is an important part of high-speed digital designs. In order to meet the need of high operation speed and low power voltage supply, the impedance of PDN should be lower than the target impedance of the design requirement. Decoupling capacitors are added on the PCB to lower the PDN impedance. The PCB PDN design is often guided by design rules and experience. In this paper, commonly-used PCB PDN designs are analyzed and categorized based on inductance contribution from specific portions of the current path. Then, the inductance components are quantified for different parts of the geometry in different designs.
An approach is presented for power integrity analysis on multi-layer printed circuit boards in th... more An approach is presented for power integrity analysis on multi-layer printed circuit boards in this paper. Two critical current paths are analyzed. Inductance decomposition is applied to identify the critical parameters that can influence the PDN input impedance. Two types of stack-ups are used to perform sensitivity analysis to illustrate the effectiveness of PDN design guidelines. Based on the analysis of the inductance contribution from different blocks in the PCB PDN, a systematic approach to obtain a complete understanding of PDN behavior is proposed. The approach can be used to provide design guidance in PDN design practice.
2017 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI), 2017
Statistical link analysis and link budget calculation is the essential part for current high-spee... more Statistical link analysis and link budget calculation is the essential part for current high-speed system design. Because of the difficulty of low bit-error rate (BER) simulation at SPICE transient solver, several methods were proposed to simulate low BER in a short time. Single-bit response (SBR) method is the most basic method; it uses SBR to construct the arbitrary waveform under the assumption of linear and time-invariant (LTI) system. However it cannot be applied to real system because I/O drivers are nonlinear. There exists a method to include these nonlinearity of real system, which is called as multiple-edge response (MER) method. There's a few paper to explain MER method, but no paper covers statistical analysis for the real system including ISI, x-talk, and power noise. In this paper, we demonstrate MER method for simple, but real HBM channel and also shows calculation burden of MER as the number of channels increase or MER order increases. Additionally, simple concept is proposed to apply MER on real HBM channel with more than a thousand I/Os.
2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI), 2018
The paper applies the combined SI-PI co-simulation to on chip high speed interconnects. A complet... more The paper applies the combined SI-PI co-simulation to on chip high speed interconnects. A complete model of chip and interposer PDN is developed and, together to a lumped model of the PCB and package PDN, it is employed to supply I/O drivers for HBM traces laid out on silicon interposer. A comprehensive analysis is carried out highlighting the impact of the decoupling capacitor placement and their corresponding parasitic inductance on the supply voltage ripple and on the output eye diagram at the signal receivers.
Application of the Thru-Reflect-Line (TRL) calibration to time domain measurements of S-parameter... more Application of the Thru-Reflect-Line (TRL) calibration to time domain measurements of S-parameters (t-TRL) allows for significantly increasing an accuracy of the obtained results. However, the accuracy of the t-TRL is still lower than that of the frequency domain vector network analyzers (VNA). There are two main sources of inaccuracies in the t-TRL calibration: random errors, such as an additive noise and jitter, and systematic errors associated with cables, connectors, and port mismatches. The paper addresses these two types of errors by proper selection of the number of sampling points, waveform averages, and record time. The PCB dielectric parameters extraction tool based on TDR/TDT measurements together with the t-TRL calibration has been developed
The injector of the European XFEL was initially designed for the operation with 1nC bunch charges... more The injector of the European XFEL was initially designed for the operation with 1nC bunch charges [1]. Later the flexibility of the nominal design of the injector with respect to the bunch charge was studied and extended also for smaller bunch charges down to 20pC [2]. A very tempting upgrade of this extension would be the operation of the European XFEL with different charges in the same train. It would make it suitable also for the experiments which require simultaneously different SASE pulse length or radiation power. In this paper we have investigated the possibility of the operation of different charges in the bunch train for the nominal design of the injector and for the case that it is extended by an additional laser system on the cathode. We have examined the problem of similarity of beam optical functions for different bunches in a train. We report also about the sensitivity of the beam optical functions on the chosen compression scenario and give an overview over the working points for the settings at the injector for single charge operation as well as combined working points for different bunch pairs.
Presented herein is an integrated test apparatus that may be used to test both Light Emitting Dio... more Presented herein is an integrated test apparatus that may be used to test both Light Emitting Diode (LED) and transceiver port features of a network device. DETAILED DESCRIPTION Many network devices, such as switches and routers, are configured to use LEDs to indicate the current status of certain device features, such as port status. These LEDs indicating the status of device features are sometimes referred to as “Status LEDs” (e.g., Port Status LED shows the current port status). These features are 100% tested during the production process, but require a set of standalone LED test stations. There are several issues with this step. In particular, network devices tend to have many ports to support different optical/Copper modules (e.g., SFP+, QSFP, and QSFP-DD) and the Status LEDs for each of these ports need to be 100% tested. In addition, the test time per network device is long and often inaccurate. The conventional testing techniques require separate test steps in the process th...
IEEE Transactions on Electromagnetic Compatibility, 2019
An evaluation is presented on the <italic>L</italic>–2<italic>L</italic> ... more An evaluation is presented on the <italic>L</italic>–2<italic>L</italic> de-embedding method for on-chip transmission lines. The method is analyzed using measurement data from two chips. Results are presented in terms of scattering parameters, as is the standard for characterizing system interconnects. The various challenges associated with on-chip modeling and measurements are discussed. Furthermore, a revised version of the <italic>L</italic>–2 <italic>L</italic> method is presented, decreasing its sensitivity to measurement noise. All de-embedding results are compared back to “ideal” simulation models for validation or disproof.
IEEE Transactions on Electromagnetic Compatibility, 2017
In this paper, a novel de-embedding methodology is proposed for through silicon via (TSV) charact... more In this paper, a novel de-embedding methodology is proposed for through silicon via (TSV) characterization by using a set of simple yet efficient test patterns. For all the test patterns, full wave models are developed and the electrical performance of the test patterns is analyzed thoroughly. Furthermore, broadband measurements are performed for the test patterns to verify the accuracy of the developed full wave models up to 40 GHz. Correlation between measurement and simulation results is discussed after optimizing the full wave models based on scanning electron microscope measurement. Analysis of measurement error is available as well. The proposed de-embedding method is applied to both the simulation and measurement results to extract the electrical characteristics of the TSV pair. Good agreement between the de-embedded results with analytical solution and the full-wave simulation for a standalone TSV pair indicates that the proposed de-embedding method works effectively up to 40 GHz. Finally, sensitivity analysis with regard to manufacturing tolerance of the test patterns to the final de-embedded results is performed.
IEEE Transactions on Instrumentation and Measurement, 2017
Novel de-embedding launch geometries and a simplified analytical procedure are proposed to extrac... more Novel de-embedding launch geometries and a simplified analytical procedure are proposed to extract the exact electromagnetic behavior of a through silicon via (TSV) pair from measured data. First, the most recent de-embedding method is reviewed and it is deeply investigated using both 3-D simulation and vector network analyzer measurements to accurately evaluate its residual error. Then, some potential sources of error are hypothesized and overcome by the proposed launch geometries based on a de-embedding plane that is able to ensure a TEM (or quasi-TEM) mode propagation. The novel launches are studied through 3-D simulations; the previous de-embedding procedure is updated to consider the fringing effect of the open-end launch, and it is simplified reducing the launch standards from three to two. The proposed launch geometries and algorithm are shown to be more accurate in the TSV pair de-embedding with respect to the method currently employed. Index Terms-De-embedding, fringing effect, through silicon vias (TSVs), vector network analyzer (VNA) measurements. I. INTRODUCTION T HROUGH silicon vias (TSVs) represent an essential element in the current 3-D integrated circuit (IC) technology for overcoming the limits of the traditional 2-D system in package in terms of bandwidth, size, and power consumption. The main advantage is that TSVs allow to stack multiple ICs while maintaining the same surface, thus minimizing the interconnect length and thus the power losses [1]-[3]. This current trend in the electronics miniaturization requires the continuous development of more sophisticated measurement techniques for testing the ICs and devices [4]-[6],
2016 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC), 2016
A transient simulation analysis is proposed for printed circuit board (PCB) power distribution ne... more A transient simulation analysis is proposed for printed circuit board (PCB) power distribution network (PDN) by using physics based circuit model. The PCB PDN is divided into different blocks. Different modeling methods are used to provide physics-based circuit models for each block. Then, Hspice simulation is used to do transient simulation for the PCB PDN based on the circuit.
2016 IEEE International Symposium on Electromagnetic Compatibility (EMC), 2016
A decomposition method for the PCB PDN voltage ripple caused by the IC switching current is devel... more A decomposition method for the PCB PDN voltage ripple caused by the IC switching current is developed based on an equivalent circuit model from a cavity model. The decomposition is presented both in frequency domain and time domain. Along with this decomposition approach, a one-to-one correspondence between the voltage ripple and the geometry is revealed. Guidelines to decrease the PCB PDN voltage ripple is also discussed and corroborated by both simulation and analytical calculation.
2016 IEEE International Symposium on Electromagnetic Compatibility (EMC), 2016
In this paper, the electrical performance of the test patterns used in the de-embedding method fo... more In this paper, the electrical performance of the test patterns used in the de-embedding method for TSV characterization was studied thoroughly. For all test patterns, full wave models were built and then analyzed based on simulated electrical performances. Equivalent circuit model analysis and parametric study results of the test patterns further demonstrate the accuracy of the full wave models. Furthermore, Scanning Electron Microscopy (SEM) measurements were taken for all the test patterns, and full wave models were optimized based on the measured dimensions. Finally, the response of the TSV pair was obtained by de-embedding the pads and traces from the TSV pair simulation with the test fixtures. Good agreement between the de-embedded results with analytical characterization and the full-wave simulation for a single TSV pair was achieved.
2016 IEEE 20th Workshop on Signal and Power Integrity (SPI), 2016
In this work the circuit segmentation approach for the modeling of Through Silicon Vias (TSV) is ... more In this work the circuit segmentation approach for the modeling of Through Silicon Vias (TSV) is extended to the presence of time domain non linear phenomena such as depletion and capacitance hysteresis. Results are shown discussing the impact of the voltage bias on the above mentioned non-linear phenomena and their combined impact on crosstalk among TSV and between TSVs and active circuits.
2015 Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC), 2015
This paper looksat the impact of consideringthe exact or approximated values for the nonlinear de... more This paper looksat the impact of consideringthe exact or approximated values for the nonlinear depletion capacitance in a TSV equivalent circuit for transient analysis. Furthermore, the effects of the time variant and nonlinear behavior of the doped bulk silicon substrate on signal propagation and crosstalk are also studied.
2015 IEEE Symposium on Electromagnetic Compatibility and Signal Integrity, 2015
Printed circuit board (PCB) power distribution network (PDN) design performance depends on the pe... more Printed circuit board (PCB) power distribution network (PDN) design performance depends on the peak voltage ripple caused by the integrated circuit (IC) switching currents. The input impedance seen by the IC looking into the PCB PDN can be calculated using a physics-based circuit model extracted from the cavity model approach. The input impedance is fitted to a simplified circuit model used to represent the PCB PDN. Using a switching current profile, the frequency domain noise voltage is found and transformed to the time domain ripple waveform which can then be used to evaluate the PDN design performance.
2009 IEEE International Symposium on Electromagnetic Compatibility, 2009
Characterizing materials used in Printed Circuit Board (PCB) manufacturing is becoming increasing... more Characterizing materials used in Printed Circuit Board (PCB) manufacturing is becoming increasingly important in link path analysis as the data rates are increasing. The material properties governing the performance of the signal passing through a transmission line are frequency-dependent. Using frequency-domain vector network analyzer (VNA) measurements and Through-Reflect-Line (TRL) calibration, these parameters can be determined accurately. But a Time-Domain Reflectometer (TDR) provides a relatively inexpensive and simple way of characterizing transmission lines, and it is easily accessible to Signal Integrity engineers. With the timedomain TRL (t-TRL) calibration technique [1], it is now possible to de-embed such discontinuities as connectors, cables, etc., in the path of the transmission line using time-domain measurements. From the calibrated results, material properties can be extracted in the same way as it is done in the frequency domain. This paper describes a t-TRL technique to obtain accurate frequency domain S-parameters from time domain measurements. The calibrated results are converted into the ABCD parameters. The propagation constant is obtained through the ABCD parameters, from which attenuation loss and phase constant are extracted. Dielectric constant is extracted from the phase constant and the total attenuation constant. Curve-fitting technique is used to split the losses into conductor and dielectric loss. Once dielectric loss is determined, loss tangent can be calculated. The results are compared for three test vehicles, and are also compared with frequency domain VNA measurements. The results from the t-TRL calibration technique are also compared with another known extraction procedure.
A modeling methodology to calculate the decoupling capacitor interconnect inductance in a multi-l... more A modeling methodology to calculate the decoupling capacitor interconnect inductance in a multi-layer PCB is proposed herein. The methodology is based on the resonant cavity model of parallel planes. The self-inductance and mutual inductance are extracted to understand the via configuration influence on the effectiveness of decoupling capacitors. A special layout of decoupling capacitor is proposed to increase the effectiveness of the decoupling capacitors by taking maximum advantage of the mutual inductance between interconnect vias with two decoupling capacitors placed in a pair, and two pairs of power and ground vias placed in alternating directions as close as possible. The number of decoupling capacitors needed can be reduced dramatically. Three PCB PDN designs are used to present the effectiveness of doublet layout in different design scenarios. Similar analysis is extended to 3-terminal decoupling capacitor layout design. The decoupling capacitor interconnect inductance of the five via layouts for 3-terminal capacitors is analyzed. The number of decoupling capacitors needed for a commercial product using the doublet layout and 3-terminal capacitor layout is compared to the design with an alternating decoupling capacitor layout to reflect the impact of the decap layout design on the PCB PDN performance.
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Papers by Brice Achkir