A VLSI system plays an important role among all other system and Verification plays important and... more A VLSI system plays an important role among all other system and Verification plays important and a huge role in a VLSI life cycle. SOC is now a days very popular due to its reusability. So this paper gives a guidance related to SOC Verification and practical approach for SOC Verification which includes fusion of verification Environment with a mix C tests for debugging embedded processor and Verilog test bench for monitors and checkers. This paper gives an idea of how a SOC is going to verify covering all its functionality using verification methodology‟s parameter such as functional coverage and code coverage. Using Verification Techniques and verification approach we can verify system level SOC.
Digital circuits are the heart of any modern microprocessor or microcontroller. Because of the va... more Digital circuits are the heart of any modern microprocessor or microcontroller. Because of the vast advantages over analog integrated circuits, digital circuits are superior in terms of speed, performance and power consumption. Nowadays, digital designs are made up using semiconductor elements like MOSFET. This provides high-speed performance. Since the last 40 years, integrated circuits have been improving as per the Moore’s law. Reduction in size of transistors introduces several problems such as SCE and DIBL. One of the possible solution is FinFET which can mitigate the problems. Using FinFET and its different topologies, positive edge-triggered D flip-flop-based ring counter is examined at 14 nm technology. Simulation is done using HSPICE and BSIM-CMG FinFET model. By changing gate geometry and substrate, results are carried out. From the results, we can conclude that quadruple gate is better option in terms of delay, average power and current compare to tri-gate and double gate...
Congestion Estimation Using Various Floorplan Techniques in 28nm Soc Design
2020 4th International Conference on Intelligent Computing and Control Systems (ICICCS), 2020
Nowadays demand for various electronic gadgets increasing swiftly. These gadgets should be as tin... more Nowadays demand for various electronic gadgets increasing swiftly. These gadgets should be as tiny as possible, consumes less power and provide better efficiency. The technology entitled "Integrated Circuit" has brought revolution in the production of electronics. The ASIC industries-key contributor of electronic systems moving towards the lower technology nodes to satisfy the demand. As the channel length decreases, device size gets decreases and package density increases. This will arise new challenges to designers. This paper present the implementation of back end design flow-PnR flow and analyzation of routing congestion by examine diverse Floorplan approaches and techniques to improve congestion. Congestion reduction is hinged on the improvement of the floorplan. This improvement has global view of congestion over the entire design. Performing congestion analysis of first floorplan approach proposing next placement move. Improving floorplan using Data Flow Analysis an...
Power is a primary consideration in many segments of today’s electronics business. The thriving m... more Power is a primary consideration in many segments of today’s electronics business. The thriving market for wireless/mobile devices such as cell phones, laptop and net book, and home entertainment electronics such as set-top boxes, digital cameras and broadband modems, is driving the need for low-power and energyefficient system-on-chip designs. Power reduction has become a vital design goal for sophisticated design applications. Power consumption in chips, especially for technology at 90nm or below, must be lowered in order to reduce the packaging, reliability, manufacturing and operational costs of these devices. In addition, energy consumption as well as the amount of power loss over time must be managed to extend the use time of battery-powered applications. So in this paper different techniques are discussed for designing of low power SoC.
Optimization of Floorplan Strategies to Reduce Timing Violation on 28nm ASIC and Scopes of Improvement for Data Center ASICs
2020 4th International Conference on Intelligent Computing and Control Systems (ICICCS), 2020
Electronics industry is moving towards rapid technology growth in which ASIC designing is the pri... more Electronics industry is moving towards rapid technology growth in which ASIC designing is the prime contributor. The data centers and various electronics systems are shrinking hence the need is to have the gadget as tiny as possible and also to have power as low as possible with high performance. With the advent of lower technology nodes, the entire electronics world is getting on a single chip making System on Chip (SoC). The miniaturization in channel length yielding smaller transistor and the high dense chip has increased challenges of engineers day by day. Also increasing demand for high-frequency design is a big challenge for the ASIC engineers. In this paper, the backend flow- PnR flow is analysed with various constraints and demonstrated with different physical design techniques to optimize the timing without compromising on the design features. Setup timing optimization is a very important and critical step of the backend design of SoCs. Many techniques are available to guid...
Test Logic Insertion for Optimization of Testing Parameters on Lower Technology Node
2020 4th International Conference on Intelligent Computing and Control Systems (ICICCS), 2020
The complexity and gate counts on chips is growing rapidly on networking application chips, becau... more The complexity and gate counts on chips is growing rapidly on networking application chips, because of s maller lithographic nodes. Design for testability (DFT) ensures no manufacturing defect on the VLS I fabricated chips. Structured DFT approaches like scan methodology, BIST, MBIST ensure quality. Nowadays, DFT itself face critical challenge due to node scaling and it affects the density of the fabricated chip. In this paper, to optimize the parameters on the 28nm technology node, like test time, test coverage, power dissipation, the area should be analysed. This is the major concern of DFT for ASIC chip designing process.
Low-density parity-check (LDPC) encoder and decoder is implemented in this paper. LDPC codes are ... more Low-density parity-check (LDPC) encoder and decoder is implemented in this paper. LDPC codes are the most powerful ECC. CCSDS standard recommends LDPC code with various code rates out of which LDPC with code rate of 7/8 is very advantageous in high data rate space missions due to low bandwidth overhead. LDPC is a quasi cyclic code with 511x511 base circulant matrices. A generic hardware architecture based on SRAA (Shift Register Adder Accumulate) encoder architecture for quasi cyclic codes is proposed in this paper. LDPC encoder encodes the data and sends it to the channel. Bit Flipping Algorithm is applied for decoding of received data. It detects and corrects the error. At the end, simulation verifies the detection and correction of errors.
In this Paper, advanced methods for DFM Verification and solutions are presented for lower nodes.... more In this Paper, advanced methods for DFM Verification and solutions are presented for lower nodes. It includes the need for Litho-Friendly Design, CMP aware Fill, Process Variation Issues and its impact on the design. Along with the DRC/LVS checks which deal with the physical verification processes, in lower technologies nodes, DFM should also be equally given importance as without it, it is impossible to achieve the silicon with maximum yield. Goal of DFM is to improve yield by minimizing defects like systematic, random and parametric defects through prevention, detection and fixing the hotspots.
VLSI systems plays important role among all other system. A nebulizer is a drug delivery device u... more VLSI systems plays important role among all other system. A nebulizer is a drug delivery device used to administer medication in the form of a mist inhaled into the lungs. The application of spray device to treat respiratory disease has been effective for long time. Asthma and chronic obstructive pulmonary disease are widely prevalent in industries part of the world. The principle of ultrasonic nebulizers is based on the vibrations of a piezoelectric crystal driven by an alternating electrical field. These periodic vibrations are characterized by their frequency, their amplitude, and their intensity, which corresponds to the energy transmitted per surface unit. When the vibration intensity is sufficient, cavitation occurs, and droplets are generated. For a given nebulizer, the vibration frequency of the piezoelectric crystal is fixed, often in the range 1 to 2.5MHzThis is different way to design nebulizer on FPGA spartan3E kit using Xilinx tool using Verilog HDL. We have tried interface ADC device.
In this Paper, advanced methods for DFM Verification and solutions are presented for lower nodes.... more In this Paper, advanced methods for DFM Verification and solutions are presented for lower nodes. It includes the need for Litho-Friendly Design, CMP aware Fill, Process Variation Issues and its impact on the design. Along with the DRC/LVS checks which deal with the physical verification processes, in lower technologies nodes, DFM should also be equally given importance as without it, it is impossible to achieve the silicon with maximum yield. Goal of DFM is to improve yield by minimizing defects like systematic, random and parametric defects through prevention, detection and fixing the hotspots.
Quadrature Phase Shift Keying (QPSK) is a modulation scheme commonly used in wireless communicati... more Quadrature Phase Shift Keying (QPSK) is a modulation scheme commonly used in wireless communication system and it's because of its ability to transmit twice the data rate for a given bandwidth. In most cases, the QPSK modulator consumes less power and bandwidth in a modern devices but for a system like satellite and mobile devices where their operations are power limited, this is a problem that needs to be fixed. The objective is to design the QPSK modulator that uses less power for operation and it should be bandwidth efficient. The proposed technique uses data stored inside a memory block to produce a symbol according to the given input data. The QPSK modulation process requires a Direct Digital Synthesizer (DDS) to produce sine and cosine wave which are used as carrier signal with the data signal to produce QPSK/BPSK output signal. The proposed modulator successfully modeled with Verilog Hardware Description Language (HDL), simulated with Xilinx Integrated Software Environment (ISE) version 14.5 software. QPSK modulation is also performed on MATLAB tool, which gives three types of waveforms. 1) In-phase component, 2) Quadrature phase, and 3) Composite of both. After that the QPSK demodulator has been developed using MATLAB tool in order to verify the functionality of the modulator.
A VLSI system plays an important role among all other system and Verification plays important and... more A VLSI system plays an important role among all other system and Verification plays important and a huge role in a VLSI life cycle. SOC is now a days very popular due to its reusability. So this paper gives a guidance related to SOC Verification and practical approach for SOC Verification which includes fusion of verification Environment with a mix C tests for debugging embedded processor and Verilog test bench for monitors and checkers. This paper gives an idea of how a SOC is going to verify covering all its functionality using verification methodology‟s parameter such as functional coverage and code coverage. Using Verification Techniques and verification approach we can verify system level SOC.
Digital circuits are the heart of any modern microprocessor or microcontroller. Because of the va... more Digital circuits are the heart of any modern microprocessor or microcontroller. Because of the vast advantages over analog integrated circuits, digital circuits are superior in terms of speed, performance and power consumption. Nowadays, digital designs are made up using semiconductor elements like MOSFET. This provides high-speed performance. Since the last 40 years, integrated circuits have been improving as per the Moore’s law. Reduction in size of transistors introduces several problems such as SCE and DIBL. One of the possible solution is FinFET which can mitigate the problems. Using FinFET and its different topologies, positive edge-triggered D flip-flop-based ring counter is examined at 14 nm technology. Simulation is done using HSPICE and BSIM-CMG FinFET model. By changing gate geometry and substrate, results are carried out. From the results, we can conclude that quadruple gate is better option in terms of delay, average power and current compare to tri-gate and double gate...
Congestion Estimation Using Various Floorplan Techniques in 28nm Soc Design
2020 4th International Conference on Intelligent Computing and Control Systems (ICICCS), 2020
Nowadays demand for various electronic gadgets increasing swiftly. These gadgets should be as tin... more Nowadays demand for various electronic gadgets increasing swiftly. These gadgets should be as tiny as possible, consumes less power and provide better efficiency. The technology entitled "Integrated Circuit" has brought revolution in the production of electronics. The ASIC industries-key contributor of electronic systems moving towards the lower technology nodes to satisfy the demand. As the channel length decreases, device size gets decreases and package density increases. This will arise new challenges to designers. This paper present the implementation of back end design flow-PnR flow and analyzation of routing congestion by examine diverse Floorplan approaches and techniques to improve congestion. Congestion reduction is hinged on the improvement of the floorplan. This improvement has global view of congestion over the entire design. Performing congestion analysis of first floorplan approach proposing next placement move. Improving floorplan using Data Flow Analysis an...
Power is a primary consideration in many segments of today’s electronics business. The thriving m... more Power is a primary consideration in many segments of today’s electronics business. The thriving market for wireless/mobile devices such as cell phones, laptop and net book, and home entertainment electronics such as set-top boxes, digital cameras and broadband modems, is driving the need for low-power and energyefficient system-on-chip designs. Power reduction has become a vital design goal for sophisticated design applications. Power consumption in chips, especially for technology at 90nm or below, must be lowered in order to reduce the packaging, reliability, manufacturing and operational costs of these devices. In addition, energy consumption as well as the amount of power loss over time must be managed to extend the use time of battery-powered applications. So in this paper different techniques are discussed for designing of low power SoC.
Optimization of Floorplan Strategies to Reduce Timing Violation on 28nm ASIC and Scopes of Improvement for Data Center ASICs
2020 4th International Conference on Intelligent Computing and Control Systems (ICICCS), 2020
Electronics industry is moving towards rapid technology growth in which ASIC designing is the pri... more Electronics industry is moving towards rapid technology growth in which ASIC designing is the prime contributor. The data centers and various electronics systems are shrinking hence the need is to have the gadget as tiny as possible and also to have power as low as possible with high performance. With the advent of lower technology nodes, the entire electronics world is getting on a single chip making System on Chip (SoC). The miniaturization in channel length yielding smaller transistor and the high dense chip has increased challenges of engineers day by day. Also increasing demand for high-frequency design is a big challenge for the ASIC engineers. In this paper, the backend flow- PnR flow is analysed with various constraints and demonstrated with different physical design techniques to optimize the timing without compromising on the design features. Setup timing optimization is a very important and critical step of the backend design of SoCs. Many techniques are available to guid...
Test Logic Insertion for Optimization of Testing Parameters on Lower Technology Node
2020 4th International Conference on Intelligent Computing and Control Systems (ICICCS), 2020
The complexity and gate counts on chips is growing rapidly on networking application chips, becau... more The complexity and gate counts on chips is growing rapidly on networking application chips, because of s maller lithographic nodes. Design for testability (DFT) ensures no manufacturing defect on the VLS I fabricated chips. Structured DFT approaches like scan methodology, BIST, MBIST ensure quality. Nowadays, DFT itself face critical challenge due to node scaling and it affects the density of the fabricated chip. In this paper, to optimize the parameters on the 28nm technology node, like test time, test coverage, power dissipation, the area should be analysed. This is the major concern of DFT for ASIC chip designing process.
Low-density parity-check (LDPC) encoder and decoder is implemented in this paper. LDPC codes are ... more Low-density parity-check (LDPC) encoder and decoder is implemented in this paper. LDPC codes are the most powerful ECC. CCSDS standard recommends LDPC code with various code rates out of which LDPC with code rate of 7/8 is very advantageous in high data rate space missions due to low bandwidth overhead. LDPC is a quasi cyclic code with 511x511 base circulant matrices. A generic hardware architecture based on SRAA (Shift Register Adder Accumulate) encoder architecture for quasi cyclic codes is proposed in this paper. LDPC encoder encodes the data and sends it to the channel. Bit Flipping Algorithm is applied for decoding of received data. It detects and corrects the error. At the end, simulation verifies the detection and correction of errors.
In this Paper, advanced methods for DFM Verification and solutions are presented for lower nodes.... more In this Paper, advanced methods for DFM Verification and solutions are presented for lower nodes. It includes the need for Litho-Friendly Design, CMP aware Fill, Process Variation Issues and its impact on the design. Along with the DRC/LVS checks which deal with the physical verification processes, in lower technologies nodes, DFM should also be equally given importance as without it, it is impossible to achieve the silicon with maximum yield. Goal of DFM is to improve yield by minimizing defects like systematic, random and parametric defects through prevention, detection and fixing the hotspots.
VLSI systems plays important role among all other system. A nebulizer is a drug delivery device u... more VLSI systems plays important role among all other system. A nebulizer is a drug delivery device used to administer medication in the form of a mist inhaled into the lungs. The application of spray device to treat respiratory disease has been effective for long time. Asthma and chronic obstructive pulmonary disease are widely prevalent in industries part of the world. The principle of ultrasonic nebulizers is based on the vibrations of a piezoelectric crystal driven by an alternating electrical field. These periodic vibrations are characterized by their frequency, their amplitude, and their intensity, which corresponds to the energy transmitted per surface unit. When the vibration intensity is sufficient, cavitation occurs, and droplets are generated. For a given nebulizer, the vibration frequency of the piezoelectric crystal is fixed, often in the range 1 to 2.5MHzThis is different way to design nebulizer on FPGA spartan3E kit using Xilinx tool using Verilog HDL. We have tried interface ADC device.
In this Paper, advanced methods for DFM Verification and solutions are presented for lower nodes.... more In this Paper, advanced methods for DFM Verification and solutions are presented for lower nodes. It includes the need for Litho-Friendly Design, CMP aware Fill, Process Variation Issues and its impact on the design. Along with the DRC/LVS checks which deal with the physical verification processes, in lower technologies nodes, DFM should also be equally given importance as without it, it is impossible to achieve the silicon with maximum yield. Goal of DFM is to improve yield by minimizing defects like systematic, random and parametric defects through prevention, detection and fixing the hotspots.
Quadrature Phase Shift Keying (QPSK) is a modulation scheme commonly used in wireless communicati... more Quadrature Phase Shift Keying (QPSK) is a modulation scheme commonly used in wireless communication system and it's because of its ability to transmit twice the data rate for a given bandwidth. In most cases, the QPSK modulator consumes less power and bandwidth in a modern devices but for a system like satellite and mobile devices where their operations are power limited, this is a problem that needs to be fixed. The objective is to design the QPSK modulator that uses less power for operation and it should be bandwidth efficient. The proposed technique uses data stored inside a memory block to produce a symbol according to the given input data. The QPSK modulation process requires a Direct Digital Synthesizer (DDS) to produce sine and cosine wave which are used as carrier signal with the data signal to produce QPSK/BPSK output signal. The proposed modulator successfully modeled with Verilog Hardware Description Language (HDL), simulated with Xilinx Integrated Software Environment (ISE) version 14.5 software. QPSK modulation is also performed on MATLAB tool, which gives three types of waveforms. 1) In-phase component, 2) Quadrature phase, and 3) Composite of both. After that the QPSK demodulator has been developed using MATLAB tool in order to verify the functionality of the modulator.
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