Papers by Reinaldo Bergamaschi
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97, 1997
Resource sharing is one of the main tasks in highlevel synthesis, and although many algorithms ha... more Resource sharing is one of the main tasks in highlevel synthesis, and although many algorithms have addressed the problem there a r e still several limitations which restrict the generality and applicability of current algorithms. Most clique-partitioning-based algorithms use local and inaccurate cost-functions which result in ine cient results. This paper presents algorithms for the resource sharing problem on registers and functional units, and shows how they overcome the limitations of existing algorithms. The main characteristics of this work are: interleaved r e gister and functional unit merging in a global clique partitioning based f r amework, accurate merging cost estimation, accurate interconnect cost estimation, relative control cost taken into account, and e cient false loop elimination. The results obtained show signi cant improvements in the delay of designs, while also minimizing area, specially for large designs with many sharing possibilities.
Embedded Java: techniques and applications (tutorial abstract)
International Conference on Computer Aided Design, 1999
Localization represents a fundamental issue in most wireless sensor network (WSN) applications. S... more Localization represents a fundamental issue in most wireless sensor network (WSN) applications. Sensed data without position information is often meaningless. Positioning is also essential for basic mechanisms composing the WSN to work efficiently. Unfortunately, propagation (e.g., indoor), battery drain, cost and size constraints preclude the utilization of GPS in most of the nodes in many WSN applications. Positioning occurs in two steps. First nodes measurements of certain physical quantities (e.g., signal time-of-arrival, angle, received power, connectivity) are obtained, then the measurements are combined using positioning techniques to deduce the location on the nodes. In this tutorial, the theoretical fundamental limits in positioning as well as practical schemes will be explained. The main positioning error sources will be illustrated. Particular emphasis will be given to distance estimation (ranging) and positioning techniques based on ultra wide bandwidth (UWB) signals due to their potential achievable accuracy and their recent adoption in the IEEE 802.15.4a standard. Some results derived from measured data in real environments will be shown to investigate the effect of system parameters on ranging and positioning accuracy. Davide Dardari received the Laurea degree in electronic engineering (summa cum laude) and the PhD degree in electronic engineering and computer science from the where he participates with WiLAB (Wireless Communications Laboratory). Recently, he has focused his activity on ultra-wide bandwidth (UWB) systems, ranging and localization techniques, as well as wireless sensor networks. He is an active member of the IEEE where he is the current secretary for the Radio Communications Committee of the IEEE Communication Society. He was co-chair of He also serves as a reviewer for Transactions/Journals and Conferences, and as a TPC member for numerous international conferences. Abstract In this tutorial students are exposed to the leading edge features of IPv6 over IEEE 802.15.4 standardization (6lowpan). The material covers not only protocol aspects, but also practical implementation aspects of 6lowpan with a short live demonstration. Issues regarding basic IPv6 and UDP compression with 6lowpan, mesh-under features, new routing activities, neighbor discovery, and backbone routing are covered.
Session details: Performance enhancement-new techniques for FPGAs and partitioning
Session details: Physical considerations in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference, 2005
The demand for electrical energy has increased making it more expensive. In computing, an environ... more The demand for electrical energy has increased making it more expensive. In computing, an environment highly dependent on energy, it is important to develop techniques which allow power savings. The evaluation of power-aware algorithms requires the measurement of actual computer power. This report presents a real power measurement framework. The framework is composed of a custom made board, which is able to capture the power consumption and is installed into a commodity computer, a data acquisition device that samples the measured values, and a piece of software that manages the framework. This work shows the steps taken to develop the framework and also presents two examples of its use. The first example power profiles a small matrix multiplication program and discusses performance and energy trade-offs. The second example uses the framework to characterize and model the power consumption of a web server delivering static web content.
Session details: Advances in low power design and power management
16th Symposium on Integrated Circuits and Systems Design
Page 1. Exclusion Relation of Out Of Ò and the Synthesis of Speed-Independent Circuits Artur Pere... more Page 1. Exclusion Relation of Out Of Ò and the Synthesis of Speed-Independent Circuits Artur Pereira, António Rui Borges and António Ferrari Departamento de Electrónica e Telecomunicaç oes Universidade de Aveiro 3810 ...
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006
Codes Isss, 2006
Synthesis for the ''''90s: Highlevel and logic synthesis techniques
Control-ow versus data-ow scheduling: Combining both approaches in an adaptive scheduling system
1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers
Durch die bekannten Untersuchungen von JORGENSEN wurde festgestellt , dals die Verbindungen des A... more Durch die bekannten Untersuchungen von JORGENSEN wurde festgestellt , dals die Verbindungen des Athylendiamins mit Platinsalzen einen sehr bedeutenden Grad von Stabilitat besitzen. Zum Beispiel gelingt es nicht , von einer Verbindung PtCI,.Ben vom Typus PtX2.4A einen Teil des Athylens weder durch Erwarmen noch durch Einwirkung von Salzsaure abzuspalten und zu der Verbindung ccPtCl,.en (vom Typus PtX2.2A) zu gelangen. Hingegen gcschieht bei den entsprechenden Ammoniakverbindungeii diese Umwandlung sehr leicht. Da das Palladium, dem Charakter seiner komplexen Salze nach, einen Ubergang von den typischen Platinametallen zur Gruppe Cu, Ni, Ag darstellt, so schieii es interessant, die Verbindung seiner Salze mit Athylendiamin einem vergleichenden Studium zu unterwerfen. Das fur unsere Versuche notige Athylendiamin haben wir nach der Methode von ROEBDAM, durch Erhitzen von C,H,Bi; mit einem fTberschufs von verdunnter, wasseriger Losung von Ammoniak in grofsen Kolben (ca. 3-4 Liter fassend) mit cinem Riickflukkiihler dargestell t. Die Kolben wurden auf Dampfbader gesetzt und nicht hoher RIS bis 60-70O erwarmt; unter solchen Bedingungen geht das Bromathylen allmahlich in Losung und nach einigen Tagen verschwindet es ganzlich, eine unbedeutende Menge eines im Wasser nicht los-
Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99, 1999
High-level synthesis operates on internal models known as control/data flow graphs r transfer-lev... more High-level synthesis operates on internal models known as control/data flow graphs r transfer-level (RTL) mode CDFG) and produces a registerof the hardware implementation for a given schedule. For high-level synthesis t-0 be efficient it has to estimate the effect that a given algorithmic decision (e.g., scheduling, allocation) will have on the final hardware implementation (after logic synthesis). Currently, this effect cannot be measured accurately because the CD-FGs are very distinct from the RTL/gate-level models used by logic synthesis, precluding interaction between high-level and logic synthesis. This paper presents a solution to this problem consisting of a novel internal model for synthesis which spans the domains of high-level and logic synthesis. This model is an RTL/gate-level network capable of representing all possible schedules that a given behavior may assume. This representation allows high-level synthesis algorithms to be formulated as logic transformations and effectively interleaved with logic synthesis.
Proceedings of the 40th conference on Design automation - DAC '03, 2003
Early power analysis for systems-on-chip (SoC) is crucial for determining the appropriate packagi... more Early power analysis for systems-on-chip (SoC) is crucial for determining the appropriate packaging and cost. This early analysis commonly relies on evaluating power formulas for all cores for multiple configurations of voltage, frequency, technology and application parameters, which is a tedious and error-prone process. This work presents a methodology and algorithms for automating the power analysis of SoCs. Given the power state machines for individual cores, this work defines the product power state machine for the whole SoC and uses formal symbolic simulation algorithms for traversing and computing the minimum and maximum power dissipated by sets of power states in the SoC.
High-Level Synthesis in a Production Environment : Methodology and Algorithms
Fundamentals and Standards in Hardware Description Languages, 1993
Ever since commercial integrated circuits (IC) became available in the early 60s, there has been ... more Ever since commercial integrated circuits (IC) became available in the early 60s, there has been a need for computer-aided design (CAD) tools. This need is a direct consequence of two problems: firstly, the need to automate repetitive, time consuming and error-prone tasks; and secondly, the explosion in design complexity which has rendered computer tools indispensable for handling vast amounts of data.
Challenges of the nanoscale era
Proceedings of the twenty-first annual symposium on Integrated circuits and system design - SBCCI '08, 2008
ABSTRACT As IC fabrication technology continues its evolution, scaling down into nanometer dimens... more ABSTRACT As IC fabrication technology continues its evolution, scaling down into nanometer dimensions, new challenges and opportunities arise for the semiconductor industry. Current device integration supports the development of highly complex systems on a chip, including digital, analog, and RF technologies. Several defying issues surface, starting at system level, where new methodologies and EDA tools must be developed to deal with the integration of heterogeneous technologies and system complexity, down to the technology level, where device models no longer rely on deterministic behavior: most relevant parameters are statistical, with subtle interactions. Power consumption not only concerns portable devices but also supercomputers, which must reduce its huge electrical bill. The test community faces new challenges, as nanodevices introduce new kinds of errors, such as an increasing sensibility to terrestrial radiations, soft errors, increasing leakage problems, and so on. Moreover, time-to-market for new electronic products is steadily decreasing, adding more pressure to the semiconductor community. This panel aims to discuss the main challenges introduced by the nanoscale era and provide some insights into future research directions.
Early and accurate analysis of SoCs
Proceedings of the 2004 international workshop on System level interconnect prediction - SLIP '04, 2004
This presentation discusses the major problems in doing early estimation of various design metric... more This presentation discusses the major problems in doing early estimation of various design metrics in systems-on-chip (SoC) design, and explains why early and accurate are usually contradictory terms. It then describes a tool for early estimation and analysis of SoCs which is capable of quickly evaluating cross-domain effects between component selection, architectural decisions, floorplanning, wiring estimation and die size prediction.
Area and performance optimizations in path-based scheduling
Proceedings of the European Conference on Design Automation.
Area and Performance Optimizations in Path-Based Scheduling Reinaldo A. Bergamaschi Raul Camposan... more Area and Performance Optimizations in Path-Based Scheduling Reinaldo A. Bergamaschi Raul Camposano IBM Research Division Thomas J. Watson Research Center Yorktown Heights, NY, USA Michael Payer Abstract This ... [13] PG Paulin and JP Knight, "Force-directed ...
Verification of Synchronous Sequential Circuits Obtained from Algorithmic Specifications
Computer Hardware Description Languages and their Applications, 1991
Abstract High-level synthesis systems take as input algorithmic, rather than declarative, specifi... more Abstract High-level synthesis systems take as input algorithmic, rather than declarative, specifications. To prove the correctness of the hardware designs they produce, one must say precisely what such specifications mean. An inherent difficulty in this respect is that these specifications are typically incomplete: they do not specify the exact timing of I/O operations. The exact timing is determined by high-level synthesis during scheduling, which assigns operations to clock cycles. Our approach back-annotates a specification according to the schedule chosen by the synthesis system, by adding clock statements to indicate the clock cycle boundaries. We give a formal semantics for the resulting clocked algorithmic specification. This allows us to define its I/O behavior also temporally, and to stipulate that the synthesized implementation is correct iff its I/O behavior coincides with the I/O behavior of the clocked algorithmic specification. Topics: Formal Verification, Synthesis.
Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91, 1991
Although allocation in high-level synthesis is a relatively well understood topic, little has bee... more Although allocation in high-level synthesis is a relatively well understood topic, little has been written about the details of the actual hardware generation. This paper presents a general approach for allocation using path analysis, which handles in a transparent way arbitrary complex schedules, involving loops, conditionals, and mutually exclusive registers and functional units. Allocation for path-based As-Fast-As-Possible scheduling, which includes initial allocation and global optimizations, is described in detail. Some novel problems in register, interconnection and control generation, for designs that rely partially on combinational logic control within each cycle, are discussed.
Uploads
Papers by Reinaldo Bergamaschi