Papers by Alireza Bakhtiar
Effective matching and efficient power conversion play key roles in longrange power telemetry. Th... more Effective matching and efficient power conversion play key roles in longrange power telemetry. This thesis discusses challenges and suggests solutions for long-range power telemetry with an emphasis on radio-frequency identification (RFID) applications. As a proof-of-concept a radio-frequency (RF) power harvesting system in a 0.13-µm CMOS technology is designed, fabricated, and successfully tested. The RF power harvesting system must maintain matching over the the wide operation frequency range of passive RFID tags, mandated by EPCglobal. In this work, we first analyze the series-inductor matching network and show that there is a trade-off between bandwidth and efficiency. We then derive some guidelines for matching circuit design for RFID tags. To solve the matching problem over a wide frequency range, an adaptive matching system is proposed. At the startup, this system turns on while the rest of the chip is still inactive, and automatically tunes the matching network to achieve its maximum output voltage. Then the rest of the chip wakes up and functions as normal. A new CMOS rectifier stage is also proposed. This stage is capable of efficient operation even with very low input powers. In addition, this rectifier stage can be cascaded to reach higher output voltages without significantly ii Abstract compromising the overall efficiency. Combination of low-power performance and cascadability makes this rectifier suitable for long-range RFID tags. The test setup and measurement results are also discussed in a separate chapter. The measurement results show a 50% rectifier efficiency at 4-µW input power. To the best of our knowledge, to date, this is the highest efficiency reported for rectifiers operating at such a low input power. Also, as compared to the output voltage at the nominal center frequency of the input matching network, the system shows less than 6% drop in output voltage over the entire 55-MHz bandwidth of the system which verifies the effectiveness of adaptive matching. iii I would like to thank Professor Shahriar Mirabbasi for all his guidance and support throughout this process. His patience and advice made this work possible. Thank you for this opportunity. I am also thankful to my colleague, Mohammad Sadegh Jalali, for all his support and the technical discussions that played a signicant role in my research. Also, I would like to acknowledge Dr. Roberto Rosales for his kind technical and non-technical assistance during the entire design process. Last but most certainly not least, I would like to extend my deepest appreciation to my wonderful parents, who always supported me and helped me to become who I am today. It was definitely not possible without their patience, support, and guidance. They have always been the greatest source of inspiration for me, and I dedicate this thesis to them.
... Alireza Sharif Bakhtiar, M. Sadegh Jalali, and Shahriar Mirabbasi Department of Electrical an... more ... Alireza Sharif Bakhtiar, M. Sadegh Jalali, and Shahriar Mirabbasi Department of Electrical and Computer Engineering University of British Columbia ... ACKNOWLEDGMENTS The authors would like to thank Dr. Roberto Rosales and Roozbeh Mehrabadi from SoC Lab at UBC for ...
... Mohammad Sadegh Jalali, Alireza Sharif Bakhtiar, Shahriar Mirabbasi Department of Electrical ... more ... Mohammad Sadegh Jalali, Alireza Sharif Bakhtiar, Shahriar Mirabbasi Department of Electrical and Computer Engineering University of British ... ACKNOWLEDGEMENTS The authors would like to thank Dr. Roberto Rosales and Roozbeh Mehrabadi for their technical and CAD ...
In this paper, an RF power harvesting system with automatic input tuning for long-range RFID tags... more In this paper, an RF power harvesting system with automatic input tuning for long-range RFID tags is described. The system uses a high quality factor LC-matching network to boost the voltage of the received RF signal. Then a new high-efficiency voltage rectifier is used to extract DC voltage from the signal. In order to maximize the voltage gain of the
In this paper, a hybrid phase and frequency detector (PFD) for phase-locked loop (PLL) based cloc... more In this paper, a hybrid phase and frequency detector (PFD) for phase-locked loop (PLL) based clock and data recovery (CDR) applications is presented. The PFD starts the phase detection process in a binary mode, for a faster acquisition time and a higher pull in range, and after the binary PLL locks, the PD switches to the linear mode of operation
IEEE Journal of Solid-State Circuits
A flip-chip co-packaged linear transimpedance amplifier (TIA) in 16-nm fin field effect transisto... more A flip-chip co-packaged linear transimpedance amplifier (TIA) in 16-nm fin field effect transistor (FinFET) CMOS demonstrating 112-Gb/s four-level pulse-amplitude modulation (4-PAM) with -8.2-dBm sensitivity is presented in support for optical receivers required in the next-generation intradata center links. A proposed three-stage TIA is comprised of a shunt-feedback stage followed by digitally programmable continuous-time linear equalizers (CTLEs) and a variable gain amplifier (VGA). Broadband low-noise design is achieved by having the first stage with much lower bandwidth (BW) followed by the proposed BW recovering CTLEs. A low-power design is supported by the inverter-based single-ended architecture with a single-ended-to-pseudo-differential conversion in the last stage. TIA's BW extension is further supported by optimizing the photodiode-to-receiver (PD-to-RX) interconnect and utilizing several inductive peaking techniques. It achieves 63-dB gain, 32-GHz BW, and an average input-referred current noise density of 16.9 pA/ √ Hz while operating at 0.9-V supply and consuming 47-mW power. Opto-electrical measurements are performed on a co-packaged prototype comprised of identical proposed TIAs in CMOS with combinations of various commercial PDs and PD-to-RX interconnect lengths confirming 112-Gb/s 4-PAM reception meeting pre-forward error correction (FEC) symbol error rate (SER) of 4.8 × 10 -4 without any post-equalization. Index Terms-100 Gb/s, 400 GbE, CMOS, co-packaged optical receiver front end, continuous-time linear equalizer (CTLE), fin field effect transistor (FinFET), gigabit Ethernet, inverter, low-noise broadband amplifier, optical communications, PAM-4, transimpedance amplifier (TIA). T HE Big Bang of the Internet powering 5G, artificial intelligence (AI), machine learning (ML), video conferencing, the Internet of Things (IoT), and cloud storage applications has continuously increased the demand on the Manuscript
2022 IEEE Custom Integrated Circuits Conference (CICC)
2017 IEEE Custom Integrated Circuits Conference (CICC), 2017
Emerging applications for short-reach optical communication require low-power receiver circuits i... more Emerging applications for short-reach optical communication require low-power receiver circuits in nanoscale CMOS technologies. An analysis of optical receivers with broadband input transimpedance reveals that their power consumption increases rapidly as bit-rate increases. This has motivated work on bandwidth-limited optical receiver front-ends. For example, receivers employing decision feedback equalization (DFE) and correlated-double sampling (CDS) are analyzed, showing that they significantly relax the bandwidth requirements of the analog front-ends, permitting their low-power implementation in CMOS. Finally the design of an optical receiver utilizing an integrate-anddump (ID) front-end is described. The receiver is implemented in 28nm CMOS and achieves -8.3dBm sensitivity at 20Gbps consuming 0.7pJ/b. * BER = 1e-12 * * Estimated based on average power * * * The difference with [14] is due to a mistake in reporting OMA in the original work * * * * Excluding clocking
2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019
Analog mixed-signal (AMS) receivers for 50+Gb/s PAM-4 offer lower power than ADC-DSP receivers [1... more Analog mixed-signal (AMS) receivers for 50+Gb/s PAM-4 offer lower power than ADC-DSP receivers [1]–[3]. Those using DFEs [2]–[3] suffer from relatively high power consumption due to the large number of latches needed in PAM-4 speculative DFEs. Better power efficiency can be achieved using only a CTLE [1]. However, analog front-ends (AFEs) are sensitive to variations in process, supply voltage and temperature. To combat this while accommodating links with loss exceeding 20dB, an AFE with extensive programmability is combined with an efficient genetic adaptation algorithm to select a setting that minimizes BER thus equalizing a 22dB-loss channel. The lack of a DFE, combined with a novel PAM-4 clock recovery scheme greatly reduces the number of latches required compared to previous works, resulting in 1.41pJ/bit power consumption in 7nm CMOS technology.
2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2018
A simulation methodology to accurately characterize DFEs is introduced. The methodology relies up... more A simulation methodology to accurately characterize DFEs is introduced. The methodology relies upon a few short simulations with carefully contrived input waveforms to extract the DFE's effective response in situ capturing all non-linearities and speed limitations in the feedback circuits. The method is applied to a conventional 1-tap DFE and an infinite-impulse response (IIR) DFE. Measurement results from an IIR DFE in 65 nm CMOS technology verify the methodology.
Low-power High speed optical links in CMOS
2017 IEEE Custom Integrated Circuits Conference (CICC), 2017
This paper presents a tunable equalizer to compensate for the under-damped response of VCSELs. Th... more This paper presents a tunable equalizer to compensate for the under-damped response of VCSELs. The equalizer transfer function has a pair of tunable complex zeros to cancel the complex conjugate poles in the VCSEL's electrical-optical transfer function enabling faster operation at lower VCSEL bias. A prototype was fabricated in 28nm CMOS technology. Utilizing the equalizer the prototype achieved 40Gbps operation with 0.5pJ/b power efficiency and 1.3dBm OMA.
Effective matching and efficient power conversion play key roles in longrange power telemetry. Th... more Effective matching and efficient power conversion play key roles in longrange power telemetry. This thesis discusses challenges and suggests solutions for long-range power telemetry with an emphasis on radio-frequency identification (RFID) applications. As a proof-of-concept a radio-frequency (RF) power harvesting system in a 0.13-μm CMOS technology is designed, fabricated, and successfully tested. The RF power harvesting system must maintain matching over the the wide operation frequency range of passive RFID tags, mandated by EPCglobal. In this work, we first analyze the series-inductor matching network and show that there is a trade-off between bandwidth and efficiency. We then derive some guidelines for matching circuit design for RFID tags. To solve the matching problem over a wide frequency range, an adaptive matching system is proposed. At the startup, this system turns on while the rest of the chip is still inactive, and automatically tunes the matching network to achieve it...
Design of a Power Scalable Capacitive MEMS Accelerometer Front End Colin Tse Masters of Applied S... more Design of a Power Scalable Capacitive MEMS Accelerometer Front End Colin Tse Masters of Applied Science Graduate Department of Electrical and Computer Engineering University of Toronto 2013 This thesis presents the design, implementation and fabrication for a 0.13μm interface to a capacitive MEMS accelerometer. By varying the number of amplifier slices used in concurrence based on different full scale input ranges, the analog circuitry power scales as the input range scales. Due to the oversampling nature of typical accelerometer front ends, for a full-scale input increase of N times, the analog circuitry power reduces by N times. The front end has two signal amplification stages, with the first stage power scaled. The chip is 1.15mmx1.15mm and implemented in a 0.13μm CMOS process. The design was packaged with the MEMS accelerometer chip inside a 44 pin CQFP. Measured results show an output rms noise of 63μVrms in a 100Hz bandwidth. The total analog circuitry power scales very linea...
IEEE Solid-State Circuits Letters, 2019
This letter presents a 56.25Gb/s analog-mixed signal pulse amplitude modulation (PAM)-4 receiver ... more This letter presents a 56.25Gb/s analog-mixed signal pulse amplitude modulation (PAM)-4 receiver in 7nm FinFET CMOS. The receiver uses an analog front-end (AFE) with extensive programmability and can equalize channels with up to 22.3dB loss at 14GHz. AFE settings are optimized using a genetic adaptation algorithm to find the global minima for the bit-error-rate (BER). A PAM-4 clock recovery scheme is proposed that reduces the number of required edge samplers for a PAM-4 bang-bang phase detector without degrading the jitter tolerance of the receiver. Using an analog front-end as opposed to a decision feedback equalizer (DFE) along with the proposed clock recovery scheme results in low energy consumption of 1.41pJ/bit.
IEEE Journal of Solid-State Circuits, 2016
Implementation of highly integrated optical receivers in CMOS promises low cost, but combining hi... more Implementation of highly integrated optical receivers in CMOS promises low cost, but combining high gain, low noise, high bandwidth, and low power in a CMOS transimpedance amplifier is a challenge. Fortunately, the sensitivity of an optical receiver is improved by limiting its frontend bandwidth far below the symbol rate and using equalization to eliminate the resulting intersymbol interference (ISI). Analysis reveals that when using a decision-feedback equalizer (DFE) to cancel all postcursor ISI, receiver sensitivity is optimized by taking a front-end bandwidth as low as 0.12 f bit , depending upon the frequency response and noise spectrum assumed for the front end. This paper presents a 20 Gb/s optical receiver with a front-end bandwidth of 3 GHz. The front end is designed to have an approximately first-order response, ensuring only postcursor ISI, which may be efficiently canceled with a first-order infinite-impulse response DFE (IIR-DFE). An IIR-DFE circuit is also proposed that obviates the need for an explicit full-rate multiplexor. Fabricated in 65 nm CMOS, the receiver achieves 0.705 pJ/b efficiency with the IIR-DFE consuming 150 fJ/b. Using a photodiode with 12 GHz analog bandwidth and responsivity of 0.5 A/W, the receiver has a sensitivity of -5.8 dBm optically modulated amplitude.
2015 Symposium on VLSI Circuits (VLSI Circuits), 2015
This paper describes a low power optical receiver for discrete photodiodes. The receiver utilizes... more This paper describes a low power optical receiver for discrete photodiodes. The receiver utilizes an input stage bandwidth of only 2GHz, affording high gain with low power consumption while limiting input-referred noise. The resulting ISI is eliminated and data recovered using an IIR DFE. The IIR DFE utilizes a local feedback to relax the timing criteria of the DFE loop. The 65-nm CMOS chip consumes 14.7 mW at 19.6Gbps.
2013 Optical Interconnects Conference, 2013
Three photodetector structures were simulated, fabricated and characterized at 850nm in a SiGe Bi... more Three photodetector structures were simulated, fabricated and characterized at 850nm in a SiGe BiCMOS process. The measurement and simulation results suggest that with modest equalization, multi-Gb/s communication is achievable without any special device fabrication.
Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010
In this paper, an RF power harvesting system with automatic input tuning for long-range RFID tags... more In this paper, an RF power harvesting system with automatic input tuning for long-range RFID tags is described. The system uses a high quality factor LC-matching network to boost the voltage of the received RF signal. Then a new high-efficiency voltage rectifier is used to extract DC voltage from the signal. In order to maximize the voltage gain of the
Proceedings of the 8th IEEE International NEWCAS Conference 2010, 2010
... Mohammad Sadegh Jalali, Alireza Sharif Bakhtiar, Shahriar Mirabbasi Department of Electrical ... more ... Mohammad Sadegh Jalali, Alireza Sharif Bakhtiar, Shahriar Mirabbasi Department of Electrical and Computer Engineering University of British ... ACKNOWLEDGEMENTS The authors would like to thank Dr. Roberto Rosales and Roozbeh Mehrabadi for their technical and CAD ...
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Papers by Alireza Bakhtiar