Abhijit Asati

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Papers by Abhijit Asati

Improved Implementation of PYNQ-Based FFT Hardware Accelerator

Design and Analysis of a Scan Chain in Subthreshold Region

Comparative Analysis of ST, ECRL and Static Logic Style at Different Process Technologies

2023 International Conference for Advancement in Technology (ICONAT)

Comparative Analysis of ST, ECRL and Static Logic Style at Different Process Technologies

Lightweight convolutional neural network architecture implementation using TensorFlow lite

International Journal of Information Technology

quotA Comparative Study of High Performance CMOS Multipliers Barrel Shifters and Modeling of NBTI Degradation in Nanometer Scale Digital VLSI Circuitsquot

Analysis of Logical Effort-Based Optimization in the Deep Submicron Technologies

Lecture notes in electrical engineering, Dec 4, 2022

A Novel Method for Suitable Hyperparameter Selection in an Accurate Convolutional Neural Network Architecture

Proceedings of International Conference on Data Science and Applications, 2021

Design and Implementation of Flash ADC using TIQ and Transmission Gate for High Speed Application

The main design blocks of Flash ADC includes the design of comparator, decoder and digital to ana... more The main design blocks of Flash ADC includes the design of comparator, decoder and digital to analog convertor. The design of comparator is the most critical task in this paper because the performance of ADC depends on the choice of comparator. This paper describes the design of high speed FLASH ADC using clocked digital comparator with 4-bit resolution. Analog signal is characterized by the signal whose amplitude is continuously changing with respect to time. The clock digital comparator is designed in TSMC 0.18 μm CMOS technology with supply voltage of 1.8 V. The length of transistor is fixed and depending upon the width of transistor, internal references voltages are generated in the range of 0.653 to 1.02 V. The proposed 4-bit flash ADC using CDC is designed using multiplexer based Decoder and simulated with the help of TANNER-EDA tool in TSMC 0.18 μm CMOS technology. High speed clocked digital comparator with inverter configuration is used for dynamic offset suppression. The co...

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Implementation of a High Performance Barrel Shifter Architecture using Three Different Logic Design Styles

Barrel shifters are often required for performing data shifting and rotation in many key computer... more Barrel shifters are often required for performing data shifting and rotation in many key computer operations from address decoding to computer arithmetic. In this paper we present a comparative study of various parameters like delay, power and area, for a high performance 16-bit barrel shifter VLSI implementations using three different logic design styles (conventional CMOS, transmission gate CMOS and Dual rail Domino CMOS logic) in 0.6mm, N-well CMOS process. The proposed barrel shifter implementations shows better performance as compared to implementation by R. Pereira [3].

A Review on Ultra Low Power Design Technique: Subthreshold Logic

Rapid increases in chip complexity, increasingly faster clocks and proliferation of portable devi... more Rapid increases in chip complexity, increasingly faster clocks and proliferation of portable devices have combined to make power dissipation an important design parameter. The power consumption of a system determines its heat dissipation as well as battery life. For some digital systems, power consumption has become the most critical design constraint. To satisfy the low power requirement one of the best technique sub-threshold logic is being introduced. This paper presents a complete review of recent research and explores all aspects/ constraints of subthreshold logic design technique. The paper explores basics of subthreshold, sources of power dissipation, challenges in subthreshold design, optimization methodology and various types of techniques which are currently used to implement ultra low power based circuits using subthreshold logic.

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Low-voltage, low-power SRAM circuits using subthreshold design technique

VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation, 2019

This chapter explores the design space of proposed M7T, MPT8T, M8T, M9T and MI-12T SRAM cells imp... more This chapter explores the design space of proposed M7T, MPT8T, M8T, M9T and MI-12T SRAM cells implemented at 45 nm technology node which are suitable for subthreshold operation. For quick comparison, Figure 3.45 shows the comparative design space exploration (DSE) chart of SRAM cells at 45 nm technology, respectively. The thorough analyses on the impacts of read stability, write ability, average write delay, average read delay and leakage power consumption in hold mode have been summarized in Table 3.14. The proposed memory cells exhibit improvement in performance over C6T.

Low-Area, High-Throughput Field-Programmable Gate Array Implementation of Microprocessor Without Interlocked Pipeline Stages

Lecture Notes in Electrical Engineering, 2021

Adiabatic Logic Code Converter Design at Different Sub-micron Technologies

Algorithms for intelligent systems, 2022

Design of a Static Current Simulator Using Device Matrix Approach

2012 International Symposium on Electronic System Design (ISED), 2012

ABSTRACT

Scheduling of dataflow graphs on partial reconfigurable hardware in Xilinx PR flow

2013 International Conference on Advanced Electronic Systems (ICAES), 2013

Partitioning and scheduling of dataflow graphs(DFGs) has been a matter of extensive research for ... more Partitioning and scheduling of dataflow graphs(DFGs) has been a matter of extensive research for ASIC based development. With the advent of partial reconfigurable hardware the need to schedule DFGs with restricted resources is required. In this research we test and extend the conventional scheduling algorithm suited for reconfiguration. In algorithm we restrict the flow as offered by Xilinx in PR design. The performance of such flow should be much significant than the conventional software execution flow. Hence we estimate the timing comparison of the software and the hardware flow.

Hardware software co-design using profiling and clustering

2012 International Conference on Communication, Information & Computing Technology (ICCICT), 2012

The digital system design process can be accelerated by concurrent design of hardware and softwar... more The digital system design process can be accelerated by concurrent design of hardware and software. This process requires the migration of functions that are computational extensive to hardware. This paper presents a framework for identifying such functions by proposing an algorithm. The framework uses the time profiling and clustering technique to achieve the objectives. Open source spark compiler has been used to convert functions to hardware description language The final interfacing has been done in embedded development kit.

3-D device matrix approach: A new algorithm for plotting energy band diagrams in semiconductors

2012 IEEE Students' Conference on Electrical, Electronics and Computer Science, 2012

Energy band diagram is one of the important results produced by a device simulator. In order to p... more Energy band diagram is one of the important results produced by a device simulator. In order to provide more flexibility and emphasis over this domain, an algorithm is presented which can be used to draw the device band diagram in any plane in either direction for a user specified biasing conditions. Algorithm uses a three dimensional matrix of the device,

Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis

Wireless Personal Communications

This paper proposes an area, speed and power-optimized band-pass digital signal processing filter... more This paper proposes an area, speed and power-optimized band-pass digital signal processing filter targeted for Kintex-7 Field Programmable Gate Array device. The filter was designed using MATLAB and Simulink and code generated using HDL Coder from MathWorks. The implementation was created using a novel high-level synthesis design method, which reduces pessimism associated with bit-width constraints in synthesis for inputs, outputs, and intermediate data nodes. MATLAB HDL coder generated Register Transfer Level (RTL) code was implemented on Xilinx Kintex 7 using Vivado software. The obtained results are superior to those of previous implementations for exact filter specifications. We also performed an RTL simulation for the filter and compared the functional verification results with a golden double-precision implementation in MATLAB. The results suggest that constraining the bit width and pessimism reduction has less than 1% impact on the filter accuracy within limits specified by architecture specifications.

Optimizing the Ratio of Number of Tubes in PCNTFET to NCNTFET for Digital Circuits

Journal of Microelectronics and Solid State Devices, May 18, 2018

Abstract Carbon nanotube Field Effect Transistors (CNTFET) offer various benefits as compared to ... more Abstract Carbon nanotube Field Effect Transistors (CNTFET) offer various benefits as compared to other FETs. Many circuits can be constructed using PCNTFETs (P-type CNTFET) and NCNTFETs (N-type CNTFET) similar to the PMOS and NMOS of the CMOS technology. The CNTFETs employ carbon nanotubes in the channel of the device to provide a path for the ballistic conduction of electrons. The different ratios of number of tubes in channel of the PCNTFET to the number of tubes in the channel of NCNTFET lead to different properties of the device. This paper focuses on determining the ratio of number of tubes in PCNTFET to NCNTFET which gives minimum PDP (Power Delay Product) through analyzing a circuit in which an inverter is loaded with eight inverters. Using the results a 4x4 Baugh-Wooley multiplier is constructed and its performance is compared with a multiplier constructed in a different way. Keywords: CNTFET, Inverter, 4x4 Baugh-Wooley Multiplier, Power Delay Product Cite this Article Abhinav Bhansali, Abhijit Asati. Optimizing the ratio of number of tubes in PCNTFET to NCNTFET for digital circuits. Journal of Microelectronics and Solid State Devices . 2018; 5(1): 34–40p.

Improved Implementation of PYNQ-Based FFT Hardware Accelerator

Design and Analysis of a Scan Chain in Subthreshold Region

Comparative Analysis of ST, ECRL and Static Logic Style at Different Process Technologies

2023 International Conference for Advancement in Technology (ICONAT)

Comparative Analysis of ST, ECRL and Static Logic Style at Different Process Technologies

Lightweight convolutional neural network architecture implementation using TensorFlow lite

International Journal of Information Technology

quotA Comparative Study of High Performance CMOS Multipliers Barrel Shifters and Modeling of NBTI Degradation in Nanometer Scale Digital VLSI Circuitsquot

Analysis of Logical Effort-Based Optimization in the Deep Submicron Technologies

Lecture notes in electrical engineering, Dec 4, 2022

A Novel Method for Suitable Hyperparameter Selection in an Accurate Convolutional Neural Network Architecture

Proceedings of International Conference on Data Science and Applications, 2021

Design and Implementation of Flash ADC using TIQ and Transmission Gate for High Speed Application

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Implementation of a High Performance Barrel Shifter Architecture using Three Different Logic Design Styles

A Review on Ultra Low Power Design Technique: Subthreshold Logic

Download

Low-voltage, low-power SRAM circuits using subthreshold design technique

VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation, 2019

Low-Area, High-Throughput Field-Programmable Gate Array Implementation of Microprocessor Without Interlocked Pipeline Stages

Lecture Notes in Electrical Engineering, 2021

Adiabatic Logic Code Converter Design at Different Sub-micron Technologies

Algorithms for intelligent systems, 2022

Design of a Static Current Simulator Using Device Matrix Approach

2012 International Symposium on Electronic System Design (ISED), 2012

ABSTRACT

Scheduling of dataflow graphs on partial reconfigurable hardware in Xilinx PR flow

2013 International Conference on Advanced Electronic Systems (ICAES), 2013

Hardware software co-design using profiling and clustering

2012 International Conference on Communication, Information & Computing Technology (ICCICT), 2012

3-D device matrix approach: A new algorithm for plotting energy band diagrams in semiconductors

2012 IEEE Students' Conference on Electrical, Electronics and Computer Science, 2012

Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis

Wireless Personal Communications

Optimizing the Ratio of Number of Tubes in PCNTFET to NCNTFET for Digital Circuits

Journal of Microelectronics and Solid State Devices, May 18, 2018

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