Proceedings of the Conference on Design Automation and Test in Europe, 2008
Embedded systems are becoming increasingly complex. Besides the additional processing capabilitie... more Embedded systems are becoming increasingly complex. Besides the additional processing capabilities, they are characterized by high diversity of computational models coexisting in a single device. Although reconfigurable architectures have already shown to be a potential solution for such systems, they just present significant speedups of very specific dataflow oriented kernels. Furthermore, reconfigurable fabric is still withheld by the need of special tools and compilers, clearly not sustaining backward software compatibility. In this paper, we propose a new technique to optimize both dataflow and control-flow oriented code in a totally transparent process, without the need of any modification in the source or binary codes. For that, we have developed a Binary Translation algorithm implemented in hardware, which works in parallel to a MIPS processor. The proposed mechanism is responsible for transforming sequences of instructions at runtime to be executed on a dynamic coarse-grain reconfigurable array, supporting speculative execution. Executing the MIBench suite, we show performance improvements of up to 2.5 times, while reducing 1.7 times the required energy, using trivial hardware resources.
2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Because of technology scaling, the soft error rate has been increasing in digital circuits, which... more Because of technology scaling, the soft error rate has been increasing in digital circuits, which in turn affects system reliability. Therefore, modern processors, including VLIW architectures, must have means to mitigate such effects to guarantee reliable computation. In this scenario, our work proposes two new low overhead fault tolerance approaches, with zero latency detection, that correct soft errors in the pipelines of a configurable VLIW processor. Each approach has a distinct way to detect errors, but they both utilize the same rollback mechanism. The first utilizes redundant hardware by having specialized duplicated pipelines. The second uses idle issue slots to execute duplicated instructions and does this by first identifying phases within an application. Our implementation does not require changes to the binary code and has negligible performance losses. It has 50% of area overhead with 35% power dissipation for the full pipeline duplication, and only 7% of extra area when using idle resources. We compared our approach to related work and demonstrate that we are more efficient when one considers the area, performance, power dissipation and error coverage altogether.
This paper presents a pioneer VLIW architecture of a native Java processor. We show that, thanks ... more This paper presents a pioneer VLIW architecture of a native Java processor. We show that, thanks to the specific stack architecture and to the use of the VLIW technique, one is able to obtain a meaningful reduction of energy consumption, with small area overhead, when compared to other ways of executing Java in hardware. The underlying technique is based on the reuse of memory access instructions, hence reducing power during memory or cache accesses. The architecture is validated for some complex embedded applications like IMDCT computation and other data processing benchmarks. Up to 3 times of savings in energy consumption is presented, when comparing the pipelined Java architecture against a VLIW version of the same processor
2015 IEEE Computer Society Annual Symposium on VLSI, 2015
ABSTRACT Thread-level parallelism (TLP) exploitation for embedded systems has been a challenge fo... more ABSTRACT Thread-level parallelism (TLP) exploitation for embedded systems has been a challenge for software developers: while it is necessary to take advantage of the availability of multiple cores, it is also mandatory to consume less energy. To speed up the development process and make it as transparent as possible, software designers use parallel programming interfaces (PPIs). However, as will be shown in this paper, each one implements different ways to exchange data, influencing performance, energy consumption and energy-delay product (EDP), which varies across different embedded processors. By evaluating four PPIs and three multicore processors, we demonstrate that it is possible to save up to 62% in energy consumption and achieve up to 88% of EDP improvements by just switching the PPI; and that the efficiency (i.e., the best possible use of the available resources) decreases as the number of threads increases in almost all cases, but at distinct rates.
2015 IEEE 39th Annual Computer Software and Applications Conference, 2015
ABSTRACT Embedded systems are becoming increasingly complex and, due to their tight energy requir... more ABSTRACT Embedded systems are becoming increasingly complex and, due to their tight energy requirements, all the available resources must be used in the best possible way. However, Android, the most used software platform for embedded systems, features a virtual machine to run applications. Even though it ensures flexibility so the application can execute on different underlying architectures without the need for recompilation, it burdens the system because of the introduction of an extra software layer. Considering this scenario, through the development of an extension of the Android QEMU emulator and a specific benchmark set, this work evaluates the significance of the virtual machine by comparing applications written in Java and in native language. We show that, given a fixed energy budget, a different amount of applications can be executed depending the way they were implemented. We also demonstrate that this difference varies according to the processor, by executing the applications on all officially supported Android architectures (Intel x86, ARM, and MIPS). Therefore, even though the Virtual Machine provides total transparency to the software developer, he/she must be aware of it and the underlying target microarchitecture at early designs stages so as to build a low-energy application.
2015 IEEE 39th Annual Computer Software and Applications Conference, 2015
Thread-Level Parallelism (TLP) exploitation for embedded systems has been a challenge for softwar... more Thread-Level Parallelism (TLP) exploitation for embedded systems has been a challenge for software developers: while it is necessary to take advantage of the availability of multiple cores, it is also mandatory to consume less energy. To speed up the development process and make it as transparent as possible, software designers use Parallel Programming Interfaces (PPIs). However, as will be shown in this paper, each PPI implements different ways to exchange data using shared memory regions, influencing performance, energy consumption and Energy-Delay Product (EDP), which varies across different embedded processors. By evaluating four PPIs and three multicore processors (ARM A8, A9 and Intel Atom), we demonstrate that by simply switching PPI it is possible to save up to 59% in energy consumption and achieve up to 85% of EDP improvements, in the most significant case. We also show that the efficiency (i.e., the best possible use of the available resources) decreases as the number of threads increases in almost all cases, but at distinct rates.
This paper discusses a test method for the wrappers present in a network-on-chip. After the test ... more This paper discusses a test method for the wrappers present in a network-on-chip. After the test vectors are defined for the wrapper, the structure of the network is reused to deliver such vectors with minimum extra hardware at system level. The wrapper structure is further slightly modified to receive and process each vector correctly. Experimental results show that the required area overhead at each wrapper has a very small impact on the system area. Moreover, the time required to test all wrappers in the network is also minimal, if compared to the system test time.
Thread-level parallelism (TLP) exploitation for embedded systems has been a challenge for softwar... more Thread-level parallelism (TLP) exploitation for embedded systems has been a challenge for software developers: while it is necessary to take advantage of the availability of multiple cores, it is also mandatory to consume less energy. To speed up the development process and make it as transparent as possible, software designers use parallel programming interfaces (PPIs). However, as will be shown in this paper, each one implements different ways to exchange data, influencing performance, energy consumption and energy-delay product (EDP), which varies across different embedded processors. By evaluating four PPIs and three multicore processors, we demonstrate that it is possible to save up to 62% in energy consumption and achieve up to 88% of EDP improvements by just switching the PPI; and that the efficiency (i.e., the best possible use of the available resources) decreases as the number of threads increases in almost all cases, but at distinct rates.
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015
Energy consumption in multicore embedded systems has become a constant concern. Thread-Level Para... more Energy consumption in multicore embedded systems has become a constant concern. Thread-Level Parallelism exploitation may reduce energy consumption because it saves static power consumption of the processor, since performance is obtained. However, as will be shown in this paper, the influence of the static power on the energy consumption and Energy-Delay Product will depend on how significant it is in the processor. By evaluating different levels of static power in the respect to the total power consumption in two embedded processors (ARM and Atom), we demonstrate that if the right value of static power consumption is tuned during the designing and manufacturing, it is possible to save up 35% in energy consumption and achieve up to 20% of improvements in the EDP efficiency (i.e., the best possible use of the available resources). We also show that the more communication the parallel application has, the lower is the impact of static power of the processor in the total energy consumption.
Java, with its advantages as being an overspread multiplatform object oriented language, has been... more Java, with its advantages as being an overspread multiplatform object oriented language, has been gaining popularity in the embedded system market over the years. However, because of its extra layer of interpretation, it is also believed that it is a slow language while being executed. Nevertheless, when this execution is done directly in hardware, Java advantages caused by its stack nature start to appear. One of these advantages concerns memory utilization, impacting in less accesses and cache misses. In this work we analyze this impact in performance and energy con-sumption, comparing a Java processor with a RISC one based on a MIPS architecture with similar characteristics.
Proceedings of the Conference on Design Automation and Test in Europe, 2008
Embedded systems are becoming increasingly complex. Besides the additional processing capabilitie... more Embedded systems are becoming increasingly complex. Besides the additional processing capabilities, they are characterized by high diversity of computational models coexisting in a single device. Although reconfigurable architectures have already shown to be a potential solution for such systems, they just present significant speedups of very specific dataflow oriented kernels. Furthermore, reconfigurable fabric is still withheld by the need of special tools and compilers, clearly not sustaining backward software compatibility. In this paper, we propose a new technique to optimize both dataflow and control-flow oriented code in a totally transparent process, without the need of any modification in the source or binary codes. For that, we have developed a Binary Translation algorithm implemented in hardware, which works in parallel to a MIPS processor. The proposed mechanism is responsible for transforming sequences of instructions at runtime to be executed on a dynamic coarse-grain reconfigurable array, supporting speculative execution. Executing the MIBench suite, we show performance improvements of up to 2.5 times, while reducing 1.7 times the required energy, using trivial hardware resources.
2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Because of technology scaling, the soft error rate has been increasing in digital circuits, which... more Because of technology scaling, the soft error rate has been increasing in digital circuits, which in turn affects system reliability. Therefore, modern processors, including VLIW architectures, must have means to mitigate such effects to guarantee reliable computation. In this scenario, our work proposes two new low overhead fault tolerance approaches, with zero latency detection, that correct soft errors in the pipelines of a configurable VLIW processor. Each approach has a distinct way to detect errors, but they both utilize the same rollback mechanism. The first utilizes redundant hardware by having specialized duplicated pipelines. The second uses idle issue slots to execute duplicated instructions and does this by first identifying phases within an application. Our implementation does not require changes to the binary code and has negligible performance losses. It has 50% of area overhead with 35% power dissipation for the full pipeline duplication, and only 7% of extra area when using idle resources. We compared our approach to related work and demonstrate that we are more efficient when one considers the area, performance, power dissipation and error coverage altogether.
This paper presents a pioneer VLIW architecture of a native Java processor. We show that, thanks ... more This paper presents a pioneer VLIW architecture of a native Java processor. We show that, thanks to the specific stack architecture and to the use of the VLIW technique, one is able to obtain a meaningful reduction of energy consumption, with small area overhead, when compared to other ways of executing Java in hardware. The underlying technique is based on the reuse of memory access instructions, hence reducing power during memory or cache accesses. The architecture is validated for some complex embedded applications like IMDCT computation and other data processing benchmarks. Up to 3 times of savings in energy consumption is presented, when comparing the pipelined Java architecture against a VLIW version of the same processor
2015 IEEE Computer Society Annual Symposium on VLSI, 2015
ABSTRACT Thread-level parallelism (TLP) exploitation for embedded systems has been a challenge fo... more ABSTRACT Thread-level parallelism (TLP) exploitation for embedded systems has been a challenge for software developers: while it is necessary to take advantage of the availability of multiple cores, it is also mandatory to consume less energy. To speed up the development process and make it as transparent as possible, software designers use parallel programming interfaces (PPIs). However, as will be shown in this paper, each one implements different ways to exchange data, influencing performance, energy consumption and energy-delay product (EDP), which varies across different embedded processors. By evaluating four PPIs and three multicore processors, we demonstrate that it is possible to save up to 62% in energy consumption and achieve up to 88% of EDP improvements by just switching the PPI; and that the efficiency (i.e., the best possible use of the available resources) decreases as the number of threads increases in almost all cases, but at distinct rates.
2015 IEEE 39th Annual Computer Software and Applications Conference, 2015
ABSTRACT Embedded systems are becoming increasingly complex and, due to their tight energy requir... more ABSTRACT Embedded systems are becoming increasingly complex and, due to their tight energy requirements, all the available resources must be used in the best possible way. However, Android, the most used software platform for embedded systems, features a virtual machine to run applications. Even though it ensures flexibility so the application can execute on different underlying architectures without the need for recompilation, it burdens the system because of the introduction of an extra software layer. Considering this scenario, through the development of an extension of the Android QEMU emulator and a specific benchmark set, this work evaluates the significance of the virtual machine by comparing applications written in Java and in native language. We show that, given a fixed energy budget, a different amount of applications can be executed depending the way they were implemented. We also demonstrate that this difference varies according to the processor, by executing the applications on all officially supported Android architectures (Intel x86, ARM, and MIPS). Therefore, even though the Virtual Machine provides total transparency to the software developer, he/she must be aware of it and the underlying target microarchitecture at early designs stages so as to build a low-energy application.
2015 IEEE 39th Annual Computer Software and Applications Conference, 2015
Thread-Level Parallelism (TLP) exploitation for embedded systems has been a challenge for softwar... more Thread-Level Parallelism (TLP) exploitation for embedded systems has been a challenge for software developers: while it is necessary to take advantage of the availability of multiple cores, it is also mandatory to consume less energy. To speed up the development process and make it as transparent as possible, software designers use Parallel Programming Interfaces (PPIs). However, as will be shown in this paper, each PPI implements different ways to exchange data using shared memory regions, influencing performance, energy consumption and Energy-Delay Product (EDP), which varies across different embedded processors. By evaluating four PPIs and three multicore processors (ARM A8, A9 and Intel Atom), we demonstrate that by simply switching PPI it is possible to save up to 59% in energy consumption and achieve up to 85% of EDP improvements, in the most significant case. We also show that the efficiency (i.e., the best possible use of the available resources) decreases as the number of threads increases in almost all cases, but at distinct rates.
This paper discusses a test method for the wrappers present in a network-on-chip. After the test ... more This paper discusses a test method for the wrappers present in a network-on-chip. After the test vectors are defined for the wrapper, the structure of the network is reused to deliver such vectors with minimum extra hardware at system level. The wrapper structure is further slightly modified to receive and process each vector correctly. Experimental results show that the required area overhead at each wrapper has a very small impact on the system area. Moreover, the time required to test all wrappers in the network is also minimal, if compared to the system test time.
Thread-level parallelism (TLP) exploitation for embedded systems has been a challenge for softwar... more Thread-level parallelism (TLP) exploitation for embedded systems has been a challenge for software developers: while it is necessary to take advantage of the availability of multiple cores, it is also mandatory to consume less energy. To speed up the development process and make it as transparent as possible, software designers use parallel programming interfaces (PPIs). However, as will be shown in this paper, each one implements different ways to exchange data, influencing performance, energy consumption and energy-delay product (EDP), which varies across different embedded processors. By evaluating four PPIs and three multicore processors, we demonstrate that it is possible to save up to 62% in energy consumption and achieve up to 88% of EDP improvements by just switching the PPI; and that the efficiency (i.e., the best possible use of the available resources) decreases as the number of threads increases in almost all cases, but at distinct rates.
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015
Energy consumption in multicore embedded systems has become a constant concern. Thread-Level Para... more Energy consumption in multicore embedded systems has become a constant concern. Thread-Level Parallelism exploitation may reduce energy consumption because it saves static power consumption of the processor, since performance is obtained. However, as will be shown in this paper, the influence of the static power on the energy consumption and Energy-Delay Product will depend on how significant it is in the processor. By evaluating different levels of static power in the respect to the total power consumption in two embedded processors (ARM and Atom), we demonstrate that if the right value of static power consumption is tuned during the designing and manufacturing, it is possible to save up 35% in energy consumption and achieve up to 20% of improvements in the EDP efficiency (i.e., the best possible use of the available resources). We also show that the more communication the parallel application has, the lower is the impact of static power of the processor in the total energy consumption.
Java, with its advantages as being an overspread multiplatform object oriented language, has been... more Java, with its advantages as being an overspread multiplatform object oriented language, has been gaining popularity in the embedded system market over the years. However, because of its extra layer of interpretation, it is also believed that it is a slow language while being executed. Nevertheless, when this execution is done directly in hardware, Java advantages caused by its stack nature start to appear. One of these advantages concerns memory utilization, impacting in less accesses and cache misses. In this work we analyze this impact in performance and energy con-sumption, comparing a Java processor with a RISC one based on a MIPS architecture with similar characteristics.
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Papers by Antonio Beck