Anshul Kumar

Followers

Following

Public Views

George Lawson

The Australian National University

naveen noronha

Visvesvaraya Technological University

Mauro Grondona

University of Genova

Rafael Domingo Osle

University of Navarra

Isad Saric

University of Sarajevo

Richard Crawford

The University of Texas at Austin

Ziya Öniş

Koç University

Mandeep Sihmar

Kurukshetra University

Abhay Gore

Dr. Babasaheb Ambedkar Marathwada University

Chandramouli Padmanabhan

IIT Madras

Interests

Uploads

Papers by Anshul Kumar

A multiplier generator for Xilinx FPGAs

Proceedings of 9th International Conference on VLSI Design

1 Introduction High level synthesizers produce technology inde-pendent designs as network of RTL ... more

MON-923 MENIN Gene Mutation: Unity Amidst Diversity

Journal of the Endocrine Society

Introduction The MEN 1 syndrome is an enigmatic disorder, manifesting a wide spectrum of disorder... more Introduction The MEN 1 syndrome is an enigmatic disorder, manifesting a wide spectrum of disorders, in members of a family, harbouring the same gene mutation. We present one such family, with a MENIN gene mutation with marked diversity in the clinical presentation Clinical cases 1992: RB (Age: 13) presented with accelerated puberty, galactorrhoea and a lactotroph adenoma. Treated with Bromocriptine, followed by hypophysectomy and radiotherapy. He was on hormone replacement for hypopituitarism. 1996: He gained 21 kg of weight and had recurrent episodes of convulsions with unconsciousness.He had hypoglycaemia (13mg/dl; N >70), with hyperinsulinemia (58uIU/ml; N<25). MRI abdomen showed a mass (3.4 x 3.0 cm) over the tail of the pancreas for which a distal pancreatectomy was done (HPE: Neuroendocrine tumour). 2013: He had pain in the lower limbs with hypercalcemia (11.4mg%; N: 8.5-10.5) and hyperparathyroidism (329 pg/ml; N: 10-61) (MIBG Scan: parathyroid adenomas treated by bilat...

Download

Thyroid abscess: A rare case report and review of literature

Thyroid Research and Practice

Effect of Atipamezole and Yohimbine Reversal on Blood Biochemical Constituents After Epidural Xylazine or Detomidine Injection in Buffaloes

Indian Veterinary Journal, 1999

A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor

Proceedings of the Ieee International Conference on Vlsi Design, Jan 4, 2008

In this work, for the first time, we present a physically based analytical threshold voltage mode... more In this work, for the first time, we present a physically based analytical threshold voltage model for omega gate silicon nanowire transistor. This model is developed for long channel cylindrical body structure. The potential distribution at each and every point of the of the wire is derived with a closed form solution of two dimensional Poisson's equation, which is then used to model the threshold voltage. Proposed model can be treated as a generalized model, which is valid for both surround gate and semi-surround gate cylindrical transistors. The accuracy of proposed model is verified for different device geometry against the results obtained from three dimensional numerical device simulators and close agreement is observed.

Download

Hybrid Multi-FPGA Board Evaluation by permitting limited multi-hop routing

Design Automation For Embedded Systems, 2004

Multi-FPGA Boards (MFBs) have been in use for more than a decade for implementing systems requiri... more Multi-FPGA Boards (MFBs) have been in use for more than a decade for implementing systems requiring high performance and for emulation /prototyping of multimillion gate chips. It is important to develop an MFB architecture which can be used for emulation or prototyping of a large number of circuits. A key feature of an MFB is its routing architecture de®ned by its inter-Field-Programmable Gate Array (FPGA) connections. There are two types of inter-FPGA connections, namelyÐ®xed connections (FCs) connecting a pair of FPGAs through dedicated wires and programmable connections (PCs) which connect a pair of FPGAs through a programmable switch. An architecture which has a mix of both these type of connections is called a hybrid routing architecture. It has been shown in the literature [7] that a hybrid MFB architecture is more ef®cient for emulation than an architecture with only one type of connections. The cost of an MFB and delay of the emulated circuit on it depends on the number of PCs used for emulation. An objective of a designer of an MFB for circuit emulation is to minimize the required number of PCs. In this paper, we describe algorithms to evaluate the requirement of PCs for many hybrid routing architectures. The requirement of PCs can be reduced if some programmable connections are replaced by a connection using only FCs by routing through FPGAs. Such a routing is called multi-hop routing. We present an optimal and a heuristic algorithm for estimation of PCs when limited number of hops through FPGAs are permitted. The unique feature of our evaluation scheme is that it is generic and treat routing architecture as a parameter. We have used benchmark circuits as well as synthetic cloned circuits for testing our algorithms. Our heuristic algorithm is very fast and gives optimal results most of the time. Our algorithms can be used for actual routing during circuit emulation.

Download

Tissue Culture Investigation of Elaeocarpus tuberculatus—a highly valued Rudraksha

Vegetos an International Journal of Plant Research, 2006

High-Level Synthesis of a 1 Mbps Direct-Sequence Spread-Spectrum RAKE Receiver

This paper presents a case study in theuse of a chain of synthesis tools at different levels ofab... more This paper presents a case study in theuse of a chain of synthesis tools at different levels ofabstractions. In this case study, a Direct-SequenceSpread-Spectrum RAKE Receiver targeted for multimediaapplications was synthesized. Beginning witha behavioural description, synthesis was carried outtranscending various levels to finally reach the layoutlevel. The main effort was spent in doing the designtransformations at higher level to meet

Customizing Embedded Processors for Specific Applications

Complexity of embedded applications is growing rapidly. This growth is accompanied by severe impl... more Complexity of embedded applications is growing rapidly. This growth is accompanied by severe implementation contraints on cost, size, performance as well as power. This has resulted in search for expanding the architectural de-sign space for implementing such complex applications. The last decade has seen the growth of Application specific instruction processors(ASIP) as an alternative to general purpose processors on one hand and Application specific integrated circuits (ASIC) on the other. ASIPs are considerably more flexible than ASICs while being more performance and power efficient than general purpose proces-sors. The key issue in designing the ASIPs relate to customization i.e. identify the critical application characteristics which need to be supported by special hard-ware to create an application specific processor. In this paper we address two specific research problems; storage customization of a RISC processor and de-sign of clustered VLIW processor. A simple RISC proces...

Download

An automated data path synthesizer for a canonic structure, implementable in VLSI

Proceedings of the 22nd ACM/IEEE conference on Design automation - DAC '85, 1985

Page 1. AN AUTGMATED DATA PATH SYNTHESIZER FOR A CANONIC STRUCTURE, IMPLEMENTABLE XN VLSI Kumar R... more

A high-level synthesis flow for custom instruction set extensions for application-specific processors

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010

Custom instruction set extensions (ISEs) are added to an extensible base processor to provide app... more Custom instruction set extensions (ISEs) are added to an extensible base processor to provide application-specific functionality at a low cost. As only one ISE executes at a time, resources can be shared. This paper presents a new high-level synthesis flow targeting ISEs. We emphasize a new technique for resource allocation, binding, and port assignment during synthesis. Our method is derived from prior work on datapath merging, and increases area reduction by accounting for the cost of multiplexors that must be inserted into the resulting datapath to achieve multi-operational functionality.

Download

Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards

Lecture Notes in Computer Science, 2000

Multi-FPGA boards (MFBs) are extensively used by the designers for logic emulation, rapid prototy... more

Internal Representation and Behavioural Synthesis of Control Dominated Applications

In this paper we address problems encountered in behavioural synthesis of control dominated appli... more In this paper we address problems encountered in behavioural synthesis of control dominated applications that are common in telecommunications. An internal representation, optimized for capturing control dominated behaviours and a synthesis strategy that takes into account the control flow is presented. Results of applying this strategy to realistic examples is presented and compared to commercial behavioural synthesis tools.

FastFwd

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES/ISSS '10, 2010

We present an efficient emulation-based technique to accelerate architecture exploration of netwo... more We present an efficient emulation-based technique to accelerate architecture exploration of networks-on-chip (NoCs). The large design space of NoC along with its growing complexity that results in low simulation speeds on host machines have motivated the need for hardware accelerators for speeding up the simulation. For example, simulation of applications with real life problem sizes could take weeks on a

A SysML Profile for Development and Early Validation of TLM 2.0 Models

Lecture Notes in Computer Science, 2011

Abstract. Use of UML for SoC design has recently generated new in-terest and several UML profiles... more

Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units

Lecture Notes in Computer Science, 2004

Instruction Level Parallelism (ILP) machines, such as Very Long Instruction Word (VLIW) architect... more Instruction Level Parallelism (ILP) machines, such as Very Long Instruction Word (VLIW) architectures, and customised architectures are two paradigms that are used to increase the performance of processors. While a VLIW machine has multiple functional units, a customised processor is equipped with Application-specific Functional Units (AFUs). Customisation has been proved beneficial on single issue machines, but its effect on multiple issue machines remains unanswered. Is a VLIW machine powerful enough to nullify the benefit of customisation? Or are the two benefits orthogonal and can be exploited together? In this paper, we answer positively to the latter question. We experimentally prove that insertion of automatically identified AFUs can improve performance of a VLIW architecture, and allow the designer of ILP processor to trade-off either issue-width or register file size. We have customised the Trimaran architecture and toolchain framework to model AFUs accurately and discuss the challenges of adding instruction-set extension support to a legacy toolchain. AFU AFU REGFILE(Single/Clustered) INTERCONNECTION NETWORK CORE SET OF FUs

Download

High Level Design Experiences With Ideas

The Sixth International Conference on VLSI Design, 1993

ABSTRACT Not Available

Controller Synthesis in Control and Memory Centric High-Level Synthesis System

5th Biennial Baltic …, 1996

... Author: Ellervee, Peeter (KTH, Superseded Departments, Electronic Systems Design) (Electronic... more

A scheme for multiple on-chip signature checking for embedded SRAMS

Journal of Systems Architecture, 2000

Download

Recurring Pattern Identification and its Application to Instruction Set Extension

A multiplier generator for Xilinx FPGAs

Proceedings of 9th International Conference on VLSI Design

1 Introduction High level synthesizers produce technology inde-pendent designs as network of RTL ... more

MON-923 MENIN Gene Mutation: Unity Amidst Diversity

Journal of the Endocrine Society

Download

Thyroid abscess: A rare case report and review of literature

Thyroid Research and Practice

Effect of Atipamezole and Yohimbine Reversal on Blood Biochemical Constituents After Epidural Xylazine or Detomidine Injection in Buffaloes

Indian Veterinary Journal, 1999

A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor

Proceedings of the Ieee International Conference on Vlsi Design, Jan 4, 2008

Download

Hybrid Multi-FPGA Board Evaluation by permitting limited multi-hop routing

Design Automation For Embedded Systems, 2004

Download

Tissue Culture Investigation of Elaeocarpus tuberculatus—a highly valued Rudraksha

Vegetos an International Journal of Plant Research, 2006

High-Level Synthesis of a 1 Mbps Direct-Sequence Spread-Spectrum RAKE Receiver

Customizing Embedded Processors for Specific Applications

Download

An automated data path synthesizer for a canonic structure, implementable in VLSI

Proceedings of the 22nd ACM/IEEE conference on Design automation - DAC '85, 1985

Page 1. AN AUTGMATED DATA PATH SYNTHESIZER FOR A CANONIC STRUCTURE, IMPLEMENTABLE XN VLSI Kumar R... more

A high-level synthesis flow for custom instruction set extensions for application-specific processors

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010

Download

Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards

Lecture Notes in Computer Science, 2000

Multi-FPGA boards (MFBs) are extensively used by the designers for logic emulation, rapid prototy... more

Internal Representation and Behavioural Synthesis of Control Dominated Applications

FastFwd

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES/ISSS '10, 2010

A SysML Profile for Development and Early Validation of TLM 2.0 Models

Lecture Notes in Computer Science, 2011

Abstract. Use of UML for SoC design has recently generated new in-terest and several UML profiles... more

Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units

Lecture Notes in Computer Science, 2004

Download

High Level Design Experiences With Ideas

The Sixth International Conference on VLSI Design, 1993

ABSTRACT Not Available

Controller Synthesis in Control and Memory Centric High-Level Synthesis System

5th Biennial Baltic …, 1996

... Author: Ellervee, Peeter (KTH, Superseded Departments, Electronic Systems Design) (Electronic... more

A scheme for multiple on-chip signature checking for embedded SRAMS

Journal of Systems Architecture, 2000

Download

Recurring Pattern Identification and its Application to Instruction Set Extension

Anshul Kumar

Related Authors

Uploads

Papers by Anshul Kumar

Log In