Papers by Anila Ann Varghese
Procedia Technology, 2016
Systems that are installed in harsh environment conditions are continuously exposed to radiations... more Systems that are installed in harsh environment conditions are continuously exposed to radiations, temperature variations and pressure variations which cause fast circuit degradation and malfunctioning. FPGAs are used as the core component in many such systems especially in mission critical and safety critical applications. To ensure reliable and prolonged system functioning until mission completion, proper fault recovery techniques need to be incorporated in to the system during the design phase itself. Traditional self-repairing schemes utilize spare cells to replace faulty cells. So, the number of spare cells increases with the number of faults to be repaired which creates high area overhead. Dynamic runtime partial reconfiguration has been considered to be a promising technique that helps improve the flexibility and efficiency of FPGA based systems. The key concept behind self-repairing scheme discussed in this paper is faulty module relocation to enable better use of resources and scheduling of repair for different modules to maintain system operation until mission completion or up to the required lifetime with maximum efficiency. The paper presents an efficient self-repairing scheme for FPGAs which can handle higher number of faults with better resource utilization and lesser overheads.
International Journal of Computer Applications, 2020
Complex Division is one of the most popular operations used in the field of complex numbers opera... more Complex Division is one of the most popular operations used in the field of complex numbers operations. Improving systems and applications functionality using non-decimal radix required extra processing time. Therefore, complex division attracts the attention of researchers and manufacturers aiming at improving their systems and applications. This paper proposed a new approach to reduce large pre-scaling tables required for radices greater than 4. The proposed approach dedicated to cope with this problem to enhance power consumption, area, and speed needed to perform this type of operations.
FPGA implementation of area-efficient single precision floating point complex divider with fault detection
Despite the applications of complex division in many fields like signal processing, control theor... more Despite the applications of complex division in many fields like signal processing, control theory, telecommunication, etc., complex division algorithms are often treated with least importance. Most of the complex division modules are to be used in environments where fault-tolerance is required. FPGA is considered as a major candidate to implement such computationally intensive tasks because of its inherent properties. Interconnect faults and logic faults are two of the major types of faults likely to occur in FPGAs. Most of the existing works on fault-tolerant complex division uses hardware redundancy technique. This work proposes a technique to implement a complex division module with fault detection capability on FPGA. A module reuse technique is used to make the architecture area-efficient. The operands are being represented in 32-bit single precision floating point format.
Procedia Technology, 2016
Systems that are installed in harsh environment conditions are continuously exposed to radiations... more Systems that are installed in harsh environment conditions are continuously exposed to radiations, temperature variations and pressure variations which cause fast circuit degradation and malfunctioning. FPGAs are used as the core component in many such systems especially in mission critical and safety critical applications. To ensure reliable and prolonged system functioning until mission completion, proper fault recovery techniques need to be incorporated in to the system during the design phase itself. Traditional self-repairing schemes utilize spare cells to replace faulty cells. So, the number of spare cells increases with the number of faults to be repaired which creates high area overhead. Dynamic runtime partial reconfiguration has been considered to be a promising technique that helps improve the flexibility and efficiency of FPGA based systems. The key concept behind self-repairing scheme discussed in this paper is faulty module relocation to enable better use of resources and scheduling of repair for different modules to maintain system operation until mission completion or up to the required lifetime with maximum efficiency. The paper presents an efficient self-repairing scheme for FPGAs which can handle higher number of faults with better resource utilization and lesser overheads.
Procedia Technology, 2016
Division algorithms are less often used unlike other arithmetic operations. But it cannot be avoi... more Division algorithms are less often used unlike other arithmetic operations. But it cannot be avoided in some systems to achieve some functionality. The division of complex numbers has got applications in fields like telecommunication, microwave systems, signal processing, GPS etc. This work proposes an area-efficient method for complex divider implementation on FPGA. The operands are represented in single precision floating point (IEEE754) format. A novel method called module reuse technique is used for reducing the device utilization on FPGA. The proposed design is analyzed using the simulation and implementation results on Xilinx Artix-7 and Virtex-5 FPGA families.
Placement Strategies for Faulty Cells in Module Relocation Based BISR Approach
Field programmable gate arrays are used as a core component in many safety and mission critical a... more Field programmable gate arrays are used as a core component in many safety and mission critical applications. In most cases these systems will be continuously exposed to radiations and change in temperature and pressure. This can result in defects within the IC which leads to malfunctioning or total system failure before mission completion. Traditionally, fault tolerance in FPGA is achieved by using spare cells to replace a faulty cell. Higher fault coverage demands more number of spares. So there is a need to develop a repair strategy with minimal hardware overhead capable to respond to defects without bothering system performance. The paper discusses a Built-in-Self-Repair (BISR) approach for FPGA based reconfigurable systems with limited number of spares, reduced area overhead, routing complexity and maximum resource utilization. The key concept used in this BISR is relocation of reconfigurable modules using dynamic runtime partial reconfiguration. This is an on-line repair metho...
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Papers by Anila Ann Varghese