Notre objectif principal était le cryptage d’information qui est devenu obligatoire pour empêcher... more Notre objectif principal était le cryptage d’information qui est devenu obligatoire pour empêcher d’éventuelles attaques ; il peut être réalisé selon deux modèles : La cryptographie à clé secrète et celle a clé publique. Dans cet article, on a opté pour un crypto système hybride combinant la rapidité d’un algorithme symétrique et la sécurité de l’algorithme asymétrique. Celui-ci sera programmé avec un logiciel VHDL est implémenté en hardware sur un circuit FPGA de la famille Virtex-4 permettent ainsi de combiner les techniques cryptographiques symétriques et asymétriques tout en exploitant au mieux les ressources offertes par les circuits FPGA et d’atteindre de bonnes performances en termes de sécurité et répondre aux contraintes des applications en temps réel. Enfin une description matérielle du VHDL de cette architecture ainsi que la simulation par ModelSim pour vérifier les résultats obtenus.
2007 International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2007
In this paper, we present the division computation by the SRT algorithm. This last is characteriz... more In this paper, we present the division computation by the SRT algorithm. This last is characterized by the linear convergence, i.e., at each iteration, one quotient digit is obtained as result. Thus, increasing a radix, the iterations number decreases, but the hardware complexity increases which involve the use of a multiplier to calculate the product of quotient digit by the
This paper presents the software implementation of Weil, Tate, Ate and Optimal Ate pairings in Ja... more This paper presents the software implementation of Weil, Tate, Ate and Optimal Ate pairings in Jacobean coordinates, over Barreto-Naehrig curve, on Virtex-5 using the MicroBlaze software processor and the ZedBoard Zynq-7000 platform using ARM hardcore processor. The most pairing functions are constructed on the same model, one execution of the Miller’s algorithm plus a final exponentiation, which can be programed with addition chain method. Our flexible system can be performed for any curve parameters.
Security management for IoT applications is a critical research field, especially when taking int... more Security management for IoT applications is a critical research field, especially when taking into account the performance variation over the very different IoT devices. In this paper, we present high-performance client/server coordinators on low-cost SoC-FPGA devices for secure IoT data collection. Security is ensured by using the Transport Layer Security (TLS) protocol based on the TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 cipher suite. The hardware architecture of the proposed coordinators is based on SW/HW co-design, implementing within the hardware accelerator core Elliptic Curve Scalar Multiplication (ECSM), which is the core operation of Elliptic Curve Cryptosystems (ECC). Meanwhile, the control of the overall TLS scheme is performed in software by an ARM Cortex-A9 microprocessor. In fact, the implementation of the ECC accelerator core around an ARM microprocessor allows not only the improvement of ECSM execution but also the performance enhancement of the overall cryptosystem....
2015 IEEE 12th International Multi-Conference on Systems, Signals & Devices (SSD15), 2015
Hash functions play an important role in modern cryptography. They are widely used to provide ser... more Hash functions play an important role in modern cryptography. They are widely used to provide services of data integrity and authentication. The hash algorithms are based on performing a number of complex operations on the input data that require a significant amount of computing resources especially when the input data are huge. Thus, hardware implementation is far more suitable, for security and performances execution issues, compared to the corresponding software implementations. Hash functions perform internal operations in an iterative fashion, which open the possibility of exploring several implementation strategies. In this paper, we are concerned by optimizing the hardware implementation of the SHA-256 algorithm on virtex-5 Xilinx FPGA. Our main contribution is to design a compact SHA-256 core and to speed-up its critical paths. These are respectively seven and six words addition. The CS (Carry Save) representation is advantageously used to overcome the carry propagation, until the last addition. Special efforts were made to design, at the LUT level, the two components (compressors 7:2 and 6:2) which are the key features of our design; their delay is data path independent and equivalent to the delay of two LUT6. The resulting architecture is compact and operates at 170 MHz with throughput of 1.36 Gbps.
2015 IEEE 12th International Multi-Conference on Systems, Signals & Devices (SSD15), 2015
AES (Advanced Encryption Standard) is a symmetric-key algorithm, meaning the same key is used for... more AES (Advanced Encryption Standard) is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting data. In this paper, we present three hardware architectures for AES, namely Serial/Serial, Parallel /Serial and Parallel/Pipelined. These architectures can be used as IP (Intellectual Property) cores in hybrid cryptosystem RSA-AES implemented on an FPGA PSoC (Programmable System on Chip). The highlights of our work are: implementing S-Box memories of AES SubBytes transformation on Slices of FPGA which reduces the hardware resources and using the Xtime() functions in the implementation of AES MixColumns transformation which accelerate its execution time. Such architectures cater to different applications and offer good tradeoffs between performances and occupied areas.
The fast and accurate evaluation of elementary functions is vitally important in many fields of s... more The fast and accurate evaluation of elementary functions is vitally important in many fields of scientific computing .We describe, in this paper, a method to calculate powering (X p) which employs table lookups and polynomial approximation, a second-order Taylor series expansion. We also present the architecture for evaluating the reciprocal on virtex-II FPGA. The virtex-II FPGA family incorporates large Blocks memories SelectRAM and provides fast arithmetic carry logic capability; we exploit these resources to implement our architecture on the XC2V80(-5) FPGA circuit with operating frequency over 31 MHz.
ABSTRACT Enhancing Montgomery modular multiplication (MMM) performances in term of speed and area... more ABSTRACT Enhancing Montgomery modular multiplication (MMM) performances in term of speed and area is crucial for public key cryptography applications. This paper presents an efficient hardware-algorithm for a high radix MMM method that exploits the features available in the Virtex-5 Xilinx FPGA. Our main contribution in this paper is to develop hardware algorithms for radix-216 number system in the FPGA to speed up the MMM. It performs an operation of two 1024-bits numbers on 64 iterations. The CS (Carry Save) representation is advantageously used to overcome the carry propagation then the iteration cycle datapath length independent. Specials efforts were made to design, at the LUT level, the compressor 6:2, which is the key feature of our design. The resulting architecture can run with clock period equivalent to the total delay of an embedded 18×18-bits and two LUT6.
Modular exponentiation is a key operation of RSA cryptosystem and is very time consuming for larg... more Modular exponentiation is a key operation of RSA cryptosystem and is very time consuming for large operands. It is performed using successive modular multiplications. This paper describes hardware architecture of the m-ary modular exponentiation with reduced number of Montgomery modular multiplications. This architecture has been implemented on FPGA circuit of Virtex-2 and presents best performances in terms of computation time and occupied resources.
2012 24th International Conference on Microelectronics (ICM), 2012
ABSTRACT Modular exponentiation is the main operation of RSA-based public-key cryptosystems. It i... more ABSTRACT Modular exponentiation is the main operation of RSA-based public-key cryptosystems. It is implemented by repeated modular multiplications which are time consuming for large operands. Accelerating the RSA requires reducing the number of modular multiplications, thus reducing the time to perform one modular multiplication.
2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era, 2009
A hardwired algorithm for computing the variable precision multiplication is presented in this pa... more A hardwired algorithm for computing the variable precision multiplication is presented in this paper. The computation method is based on the use of a parallel multiplier of size m to compute the multiplication of two numbers of nxm bits. These numbers are represented in the variable precision floating point format, but in this paper only the mantissas are considered; the
Recent Trends in Multimedia Information Processing - Proceedings of the 9th International Workshop on Systems, Signals and ImageProcessing, 2002
This paper deals with the computation of some elementary functions using piecewise Minimax approx... more This paper deals with the computation of some elementary functions using piecewise Minimax approximation and small tables. The strength of the method is Ilia1 the same schetne is uscd to compure all the elementary functions with sintdar delay and accuracy of Iulp (unit in last place). The hardware implementation of this method requires one mulliplier and one adder chosen among those available in the Virtex-II FPGA as rhey present the highest performances concerning the delay and the area. The method has been implemented in a recursive structure which operates ai ajircquency ofover than 25 Mhz.
2008 3rd International Design and Test Workshop, 2008
A new high precision serial multiplier with Most Significant Digit First (MSDF) is presented. Thi... more A new high precision serial multiplier with Most Significant Digit First (MSDF) is presented. This one uses a Borrow-Save (BS) adder to perform the reduction of large length partials products required by the multiplication of large numbers. The results are converted from BS form to the 2's complement representation by the on-the-fly conversion which let the conversion of the digit result as soon as it is obtained. It is shown that the comparison between the residual and these constants (-3/2,-1/2, 1/2 and 3/2) needed in the radix-2 on line multiplication, present problem in high precision computation. However, in the proposed method the operands are introduced digit by digit with MSDF mode and results are obtained in the same manner with fixed time delay independently of the operand size. So, this approach is advantageously used for the long multiplication computation. This method has been tested by the execution of a program developed with Maple 9.5 for several test vectors. The results of the implementation of this multiplier for several operands sizes (128,256, 512, and 1024) on Virtex-II FPGA Circuit confirm that the multiplication is performed in constant time.
2009 IEEE/ACS International Conference on Computer Systems and Applications, 2009
... Our method employs a piecewise Minimax approximation and look-up tables. ... The direct use o... more ... Our method employs a piecewise Minimax approximation and look-up tables. ... The direct use of table look-up is the fast way to evaluate elementary functions; nevertheless the memory required for the table becomes quickly prohibitive, when the precision increases. ...
Notre objectif principal était le cryptage d’information qui est devenu obligatoire pour empêcher... more Notre objectif principal était le cryptage d’information qui est devenu obligatoire pour empêcher d’éventuelles attaques ; il peut être réalisé selon deux modèles : La cryptographie à clé secrète et celle a clé publique. Dans cet article, on a opté pour un crypto système hybride combinant la rapidité d’un algorithme symétrique et la sécurité de l’algorithme asymétrique. Celui-ci sera programmé avec un logiciel VHDL est implémenté en hardware sur un circuit FPGA de la famille Virtex-4 permettent ainsi de combiner les techniques cryptographiques symétriques et asymétriques tout en exploitant au mieux les ressources offertes par les circuits FPGA et d’atteindre de bonnes performances en termes de sécurité et répondre aux contraintes des applications en temps réel. Enfin une description matérielle du VHDL de cette architecture ainsi que la simulation par ModelSim pour vérifier les résultats obtenus.
2007 International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2007
In this paper, we present the division computation by the SRT algorithm. This last is characteriz... more In this paper, we present the division computation by the SRT algorithm. This last is characterized by the linear convergence, i.e., at each iteration, one quotient digit is obtained as result. Thus, increasing a radix, the iterations number decreases, but the hardware complexity increases which involve the use of a multiplier to calculate the product of quotient digit by the
This paper presents the software implementation of Weil, Tate, Ate and Optimal Ate pairings in Ja... more This paper presents the software implementation of Weil, Tate, Ate and Optimal Ate pairings in Jacobean coordinates, over Barreto-Naehrig curve, on Virtex-5 using the MicroBlaze software processor and the ZedBoard Zynq-7000 platform using ARM hardcore processor. The most pairing functions are constructed on the same model, one execution of the Miller’s algorithm plus a final exponentiation, which can be programed with addition chain method. Our flexible system can be performed for any curve parameters.
Security management for IoT applications is a critical research field, especially when taking int... more Security management for IoT applications is a critical research field, especially when taking into account the performance variation over the very different IoT devices. In this paper, we present high-performance client/server coordinators on low-cost SoC-FPGA devices for secure IoT data collection. Security is ensured by using the Transport Layer Security (TLS) protocol based on the TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 cipher suite. The hardware architecture of the proposed coordinators is based on SW/HW co-design, implementing within the hardware accelerator core Elliptic Curve Scalar Multiplication (ECSM), which is the core operation of Elliptic Curve Cryptosystems (ECC). Meanwhile, the control of the overall TLS scheme is performed in software by an ARM Cortex-A9 microprocessor. In fact, the implementation of the ECC accelerator core around an ARM microprocessor allows not only the improvement of ECSM execution but also the performance enhancement of the overall cryptosystem....
2015 IEEE 12th International Multi-Conference on Systems, Signals & Devices (SSD15), 2015
Hash functions play an important role in modern cryptography. They are widely used to provide ser... more Hash functions play an important role in modern cryptography. They are widely used to provide services of data integrity and authentication. The hash algorithms are based on performing a number of complex operations on the input data that require a significant amount of computing resources especially when the input data are huge. Thus, hardware implementation is far more suitable, for security and performances execution issues, compared to the corresponding software implementations. Hash functions perform internal operations in an iterative fashion, which open the possibility of exploring several implementation strategies. In this paper, we are concerned by optimizing the hardware implementation of the SHA-256 algorithm on virtex-5 Xilinx FPGA. Our main contribution is to design a compact SHA-256 core and to speed-up its critical paths. These are respectively seven and six words addition. The CS (Carry Save) representation is advantageously used to overcome the carry propagation, until the last addition. Special efforts were made to design, at the LUT level, the two components (compressors 7:2 and 6:2) which are the key features of our design; their delay is data path independent and equivalent to the delay of two LUT6. The resulting architecture is compact and operates at 170 MHz with throughput of 1.36 Gbps.
2015 IEEE 12th International Multi-Conference on Systems, Signals & Devices (SSD15), 2015
AES (Advanced Encryption Standard) is a symmetric-key algorithm, meaning the same key is used for... more AES (Advanced Encryption Standard) is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting data. In this paper, we present three hardware architectures for AES, namely Serial/Serial, Parallel /Serial and Parallel/Pipelined. These architectures can be used as IP (Intellectual Property) cores in hybrid cryptosystem RSA-AES implemented on an FPGA PSoC (Programmable System on Chip). The highlights of our work are: implementing S-Box memories of AES SubBytes transformation on Slices of FPGA which reduces the hardware resources and using the Xtime() functions in the implementation of AES MixColumns transformation which accelerate its execution time. Such architectures cater to different applications and offer good tradeoffs between performances and occupied areas.
The fast and accurate evaluation of elementary functions is vitally important in many fields of s... more The fast and accurate evaluation of elementary functions is vitally important in many fields of scientific computing .We describe, in this paper, a method to calculate powering (X p) which employs table lookups and polynomial approximation, a second-order Taylor series expansion. We also present the architecture for evaluating the reciprocal on virtex-II FPGA. The virtex-II FPGA family incorporates large Blocks memories SelectRAM and provides fast arithmetic carry logic capability; we exploit these resources to implement our architecture on the XC2V80(-5) FPGA circuit with operating frequency over 31 MHz.
ABSTRACT Enhancing Montgomery modular multiplication (MMM) performances in term of speed and area... more ABSTRACT Enhancing Montgomery modular multiplication (MMM) performances in term of speed and area is crucial for public key cryptography applications. This paper presents an efficient hardware-algorithm for a high radix MMM method that exploits the features available in the Virtex-5 Xilinx FPGA. Our main contribution in this paper is to develop hardware algorithms for radix-216 number system in the FPGA to speed up the MMM. It performs an operation of two 1024-bits numbers on 64 iterations. The CS (Carry Save) representation is advantageously used to overcome the carry propagation then the iteration cycle datapath length independent. Specials efforts were made to design, at the LUT level, the compressor 6:2, which is the key feature of our design. The resulting architecture can run with clock period equivalent to the total delay of an embedded 18×18-bits and two LUT6.
Modular exponentiation is a key operation of RSA cryptosystem and is very time consuming for larg... more Modular exponentiation is a key operation of RSA cryptosystem and is very time consuming for large operands. It is performed using successive modular multiplications. This paper describes hardware architecture of the m-ary modular exponentiation with reduced number of Montgomery modular multiplications. This architecture has been implemented on FPGA circuit of Virtex-2 and presents best performances in terms of computation time and occupied resources.
2012 24th International Conference on Microelectronics (ICM), 2012
ABSTRACT Modular exponentiation is the main operation of RSA-based public-key cryptosystems. It i... more ABSTRACT Modular exponentiation is the main operation of RSA-based public-key cryptosystems. It is implemented by repeated modular multiplications which are time consuming for large operands. Accelerating the RSA requires reducing the number of modular multiplications, thus reducing the time to perform one modular multiplication.
2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era, 2009
A hardwired algorithm for computing the variable precision multiplication is presented in this pa... more A hardwired algorithm for computing the variable precision multiplication is presented in this paper. The computation method is based on the use of a parallel multiplier of size m to compute the multiplication of two numbers of nxm bits. These numbers are represented in the variable precision floating point format, but in this paper only the mantissas are considered; the
Recent Trends in Multimedia Information Processing - Proceedings of the 9th International Workshop on Systems, Signals and ImageProcessing, 2002
This paper deals with the computation of some elementary functions using piecewise Minimax approx... more This paper deals with the computation of some elementary functions using piecewise Minimax approximation and small tables. The strength of the method is Ilia1 the same schetne is uscd to compure all the elementary functions with sintdar delay and accuracy of Iulp (unit in last place). The hardware implementation of this method requires one mulliplier and one adder chosen among those available in the Virtex-II FPGA as rhey present the highest performances concerning the delay and the area. The method has been implemented in a recursive structure which operates ai ajircquency ofover than 25 Mhz.
2008 3rd International Design and Test Workshop, 2008
A new high precision serial multiplier with Most Significant Digit First (MSDF) is presented. Thi... more A new high precision serial multiplier with Most Significant Digit First (MSDF) is presented. This one uses a Borrow-Save (BS) adder to perform the reduction of large length partials products required by the multiplication of large numbers. The results are converted from BS form to the 2's complement representation by the on-the-fly conversion which let the conversion of the digit result as soon as it is obtained. It is shown that the comparison between the residual and these constants (-3/2,-1/2, 1/2 and 3/2) needed in the radix-2 on line multiplication, present problem in high precision computation. However, in the proposed method the operands are introduced digit by digit with MSDF mode and results are obtained in the same manner with fixed time delay independently of the operand size. So, this approach is advantageously used for the long multiplication computation. This method has been tested by the execution of a program developed with Maple 9.5 for several test vectors. The results of the implementation of this multiplier for several operands sizes (128,256, 512, and 1024) on Virtex-II FPGA Circuit confirm that the multiplication is performed in constant time.
2009 IEEE/ACS International Conference on Computer Systems and Applications, 2009
... Our method employs a piecewise Minimax approximation and look-up tables. ... The direct use o... more ... Our method employs a piecewise Minimax approximation and look-up tables. ... The direct use of table look-up is the fast way to evaluate elementary functions; nevertheless the memory required for the table becomes quickly prohibitive, when the precision increases. ...
Uploads
Papers by Anane Mohamed