Digital data production speeds up dramatically every day, and the need to store extensive data ri... more Digital data production speeds up dramatically every day, and the need to store extensive data rises consequently. Many storage media are used today, but only a few are capable of the required features in terms of high density, data duration, storage lifetime, and reliability. DNA-based digital data storage systems are one of the new and feature-rich media to store a massive amount of data in a very tiny volume with a strange lifetime. However, building dense and straightforward DNA storage comes with some challenges. Using manual methods to transfer and mix liquids containing DNA molecules makes this storage more error-prone. Moreover, the encoding method of digital data into DNA molecules is very crucial. This paper proposes a novel method for automatic and controllable DNA strand manipulation using a customized Digital Microfluidic Biochip (DMFB) corresponding to the CAD algorithm. Then, we offer a new approach to encoding the digital data into DNA molecules that helps error detection and correction in DNA storage while it brings efficient encoding density. Experimental results show that we can write 1.6 bits on each nucleotide with a 200-base strand which is a good density compared with other methods. In contrast, the encoding method is much simpler and easier to implement.
Digital microfluidic biochips (DMFBs) are revolutionary biomedical devices towards diagnostics an... more Digital microfluidic biochips (DMFBs) are revolutionary biomedical devices towards diagnostics and point-of-care applications; the chips provide the capability of performing wide ranges of biochemistry and laboratory procedures, offering various opportunities among which to mention are automation, miniaturization and cost-affordability of bioassays. There have been various digital microfluidic biochips architectures; the application-specific chips are mainly suited towards executing a predefined set of bioassays whereas the more flexible generalpurpose chips allow executing wide ranges of bioassays on the same architecture. Though more flexible in terms of performing various bioassays the general-purpose chips require more complicated designs compared with application-specific counterparts necessitating larger and more costly designs. This paper attempts to propose a general-purpose field-programmable pin-constrained DMFB design with improved characteristics in terms area-consumption, manufacturing cost and performance.
DNA computing is a new kind of computation for solving the complex problems with the huge degree ... more DNA computing is a new kind of computation for solving the complex problems with the huge degree of parallelism. Recently it is found that DNA-based logic systems can be useful in many of biomedical applications such as early cancer detection. DNA logic systems have been applied successfully to detect the risky patterns of nucleotide-based cancer biomarkers (microRNAs). Detection of real diseases requires the large-scale DNA-based logical systems. Therefore, large-scale DNA-based logic circuits is a crucial research topic. In this paper, an automatic design flow is proposed to facilitate the design, verification and physical implementation of multi-stage and large-scale DNA logic circuits. Digital Microfluidic Biochips (DMFB) have been used recently as a promising platform for efficient implementation of DNA-based computing systems and circuits. We used this technology as the physical platform for implementation of DNA-based circuits. Our experiments and implementations show the feasibility, accuracy, efficiency and simplicity of the proposed design flow. Final DNA reactions that are synthesized by the proposed design flow are verified and simulated with stochastic DNA-reaction simulators to prove the correctness of the proposed design flow. This design flow can open a new horizon for researchers and scientists to design, implement and evaluate the DNA-based logic systems.
The template attack is one of the most efficient attacks for exploiting the secret key. Template-... more The template attack is one of the most efficient attacks for exploiting the secret key. Template-based attack extracts a model forthe behavior of side channel information from a device which is similar to the target device and then uses this model to retrievethe correct key on the target victim device. Until now, many researchers have focused on improving the performance of templateattacks ,but recently, a few countermeasures have been proposed to protect the design against these attacks. On the other hand,researches show that regular countermeasures against these attacks are costly. Randomized shuffling in the time domain is knownas a cost-effective countermeasure against side-channel attacks that are widely used. In this article, we implemented an actualtemplate attack and proposed an efficient countermeasure against it.We focus on the time shifting method against template attack.The results show that template attack is very susceptible to this method. The performance of attack on...
Intelligent car navigation systems are planned to assist humans and route them automatically in t... more Intelligent car navigation systems are planned to assist humans and route them automatically in the roads with sufficient security and correctness. Landmark-based car navigation is a widely used technique in automotive and robot navigation. In this paper, we improved a wireless landmark-based car navigation (WLCN) algorithm to operate in multi-agent (MA) environments. The extended navigation algorithm allows the cars to overtake in uni-directional real roads. Overtaking is based on the information which the cars send to each other in the road. According to this information and using a related algorithm, cars traverse each other. Analysis of accuracy and efficiency in various states, real-time RISC-based embedded system especially for high speed movements in real roads show that, the cars are navigated easily and reliable in multi-agent environments and they can successfully do overtake. In addition to reliable navigating, calculation cost of the algorithm is acceptable for real worl...
Side-channel analysis methods can reveal the secret information of digital electronic systems by ... more Side-channel analysis methods can reveal the secret information of digital electronic systems by analyzing the dependency between the power consumption of implemented cryptographic algorithms and the secret data. Recent studies show that it is possible to gather information about power consumption from FPGAs without any physical access. High flexibilities of modern FPGAs cause that they are used for cloud accelerator in Platform as a Service (PaaS) system; however, new serious vulnerabilities emerged for these platforms. Although there are some reports about how switching activities from one region of FPGA affect other regions, details of this technique are not analyzed. In this paper, we analyzed the strength of this kind of attack and examined the impact of geometrical and electrical parameters of the victim/attacker modules on the efficiency of this attack. We utilized a Zynq-based Xilinx platform as the device under attack. Experimental results and analyses show that the distanc...
A B S T R A C T Nowadays, bulk of the designers prefer to outsource some parts of their design an... more A B S T R A C T Nowadays, bulk of the designers prefer to outsource some parts of their design and fabrication process to the third-part companies due to the reliability problems, manufacturing cost and time-to-market limitations. In this situation, there are a lot of opportunities for malicious alterations by the o-shore companies. In this paper, we proposed a new placement algorithm that hinders the hardware Trojan insertion or simplies the detection process in existence of Trojans. Experimental results show that the proposed placement improves the Trojan detectability of the attempted benchmarks against Trojan insertion more than 20% in reasonable cost in delay and wire length.
Fab-less business model in semiconductor industry has led to serious concerns about trustworthy h... more Fab-less business model in semiconductor industry has led to serious concerns about trustworthy hardware. In untrusted foundries and manufacturing companies, submitted layout may be analyzed and reverse engineered to steal the information of a design or insert malicious Trojans. Understanding the netlist topology is the ultimate goal of the reverse engineering process. In this paper, we propose a netlist encryption mechanism to hide the interconnect topology inside an IC. Moreover, new special standard cells (Wire Scrambling cells) are designed to play the role of netlist encryption. Furthermore, a design flow is proposed to insert the WS-cells inside the netlist with the aim of maximum obfuscation and minimum overhead. It is worth noting that this mechanism is fully automated with no need to detail information of the functionality and structure of the design. Our proposed mechanism is implemented in an academic physical design framework (EduCAD). Experimental results show that reverse engineering can be hindered considerably in cost of negligible overheads by 23% in area, 3.25% in delay and 14.5% in total wire length. Reverse engineering is evaluated by brute-force attack, and the learned information is 0% and the Hamming distance is approximately 50%.
A Digital Microfluidic Biochip (DMFB) offers a promising platform for medical diagnostics, DNA se... more A Digital Microfluidic Biochip (DMFB) offers a promising platform for medical diagnostics, DNA sequencing, Polymerase Chain Reaction (PCR), and drug discovery and development. Conventional Drug discovery procedures require timely and costly manned experiments with a high degree of human errors with no guarantee of success. On the other hand, DMFB can be a great solution for miniaturization, integration, automation, and cost reduction of drug discovery. DMFB can improve the parallelism of drug discovery procedures; since most procedures in drug discovery are concurrent and parallel, DMB can reduce the execution time of these bioassays. Therefore, there is a critical need to develop DMFBs to speed up the drug discovery applications and improve cost and error of these reactions. In this paper, a new architecture is used for drug discovery applications. The architecture is evaluated and compared with FPPC architecture. The experimental results prove that the new architecture is faster and cheaper than FPPC; it reduces all the important parameters such as total execution time, number of controlling pins, CAD algorithm execution time, and the area usage and its costs. There is an urgent need for collaboration between experts of drug discovery, microfluidic platform architecture and also machine learning to design a data-driven microfluidic architecture which improves the CAD algorithms by learning from prior knowledge.
Micro/Nanofluidic biochips are used to automate the clinical diagnosis, DNA sequencing, automated... more Micro/Nanofluidic biochips are used to automate the clinical diagnosis, DNA sequencing, automated drug discovery and real time bio-molecular recognition. One of attractive usages of biochips is Lab-on-chip (LOC). Lab-on-Chip technology is a promising replacement for biomedical and chemical apparatus. Two main types of microfluidic based biochips are used: continuous-flow based and digital microfluidic biochips (DMFB). In DMFBs, liquids, in the form of droplets, are controlled independently and concurrently over a two dimensional array of cells (or electrodes).Digital microfluidic biochips provide high ability to configure and fault tolerance. In this paper, a new architecture for DMFB with purpose of balancing among the parameters of flexibility, efficiency, cost, and completion time of biological experiments, is presented. In the new architecture, a FPGA-based structure is used, which increase flexibility and paralellizing assay operations. Experiments show that, the execution time of scheduling, routing, and simulation are improved in comparison with FPPC architecture about 2.54%, 18.76% and 12.52%, respectively in cost of 21% overhead in the number of controlling pins.
International Journal of Computer Theory and Engineering, 2017
Significant portion of digital design flow runtime is related to the physical design stages. Part... more Significant portion of digital design flow runtime is related to the physical design stages. Partitioning is a critical stage of physical design and its quality and runtime has considerable impact on physical design efficiency. In this paper, a new parallel partitioning algorithm is proposed and it is suitable for GPU system. In the proposed algorithm, coarsening phase of the partitioning is accelerated by parallelizing on GPU. Experimental results show that runtime can be improved up to 7x for attempted circuit with negligible quality degradation. Index Terms-GPU programming, multilevel partitioning, parallel algorithms, physical design. I. INTRODUCTION Integrated circuits complexity has been grown in last decades with exponential rate and it is predicted that this flow will be continued in future years [1], [2]. This exponential growth of modern circuits is an important challenge for computer-aided design tools because their runtime will be increased dramatically coping with this complexity growth [3], [4]. On the other hand, the gap between complexity growth and productivity of CAD tools (i.e. productivity gap) will be increased for new ultra-large systems such as system-on-chips and multi-core systems. Considerable portion of total design time is related to physical design stage. Physical design consists of some important steps such as partitioning, floor-planning, placement and routing. In Partitioning phase, design graph is partitioned to some sub-graphs to facilitate rest of algorithms. Floor-planning find location and shape of large blocks. Exact location and orientation of the standard cells are fixed in placement step and finally, the geometry of interconnects will be determined in routing stage. A bundle of physical design algorithms are NP-complete and NP-hard [5], [6]. Graph partitioning is a critical sub-stage of physical design. Quality and execution time of partitioning stage has considerable impact on total quality of design and total execution time of physical design flow. Therefore, we focused on parallelizing the graph partitioning stage to improve its runtime regarding to the partitioning quality. Many contributions are reported on parallelizing the CAD algorithms on multi-processor systems in the last years of 90's
Recent improvements in the bio-engineering area have composed wonderful opportunities to manipula... more Recent improvements in the bio-engineering area have composed wonderful opportunities to manipulate the bio-structures. Biochips are known as electronic platforms to decrease the experiment time and cost and improve the exibility and automatability of operations. Digital micro/nano uidic biochips can carry discrete droplets of experiment materials on the chip to perform the projected assays. In this paper, a new FPGA-inspired architecture is proposed for micro-uidic biochips in order to improve the con gurability and exibility of the biochip and also reduce the number of controlling pins. The simulation results show that in the proposed architecture, number of controlling pins is improved by 6.35x compared with the direct addressing method and the total experiment time is reduced by 34% compared with the eld-programmable pin-constrained method, improving con gurability and exibility.
The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012), 2012
Replacing the conventional interconnects with newer material is an effective solution for the ser... more Replacing the conventional interconnects with newer material is an effective solution for the serious problems of these interconnects, especially in FPGAs in which more than of 70% of area covered by interconnects. In this paper, using the Carbon Nanotube (CNT) interconnects in FPGAs is explored and a CNT/Metal hybrid routing architecture for large FPGAs is proposed. In the presented architecture, both CNT and metal wires are utilized such that global wires are routed by CNT and local nets are constructed by metal wires. Our experimental results show that this architecture improves critical delay, total wirelength, and total power consumption by 10.87%, 1.28%, and 4.60%, respectively of attempted benchmarks.
Modern integrated circuits consist of millions of standard cells and routing paths. In nano-scale... more Modern integrated circuits consist of millions of standard cells and routing paths. In nano-scale designs, mis-prediction is a dominant problem that may diminish the quality of physical design algorithms or even result in the disruption of the convergence of the design cycle. In this paper, a new planning methodology is presented in which a masterplan of the chip is constructed at the early levels of the physical design, preparing for the operation of the subsequent physical design stages. As a proof of concept study, the proposed planning design flow is applied to both wire planning and buffer resource planning, and the outcomes are compared against conventional contributions. Experimental results reveal considerable improvements in terms of performance, timing yield and buffer usage.
20th Iranian Conference on Electrical Engineering (ICEE2012), 2012
Automotive embedded systems are widely used in modern vehicles such as cars, aircrafts and so on.... more Automotive embedded systems are widely used in modern vehicles such as cars, aircrafts and so on. However, modeling and evaluation of these systems is very challenging because time-to-market is very short and vehicles use very different platforms with various sensors, operating systems and embedded software modules. In this paper, we propose a TrueTime-based networked automotive platform (TrueFlex) which enables modeling and simulation of processing units, operating system kernels, communication bus and sensors/actuators in realtime or non-realtime automotive systems. This platform is easily upgradeable and provides different abstraction levels for modeling of automotive embedded systems with very informative reports and graphs. This platform is implemented and evaluated in this paper to show its very useful capabilities for automotive electronic designers.
Asynchronous serial transceivers have been recently used for data serializing in large on-chip sy... more Asynchronous serial transceivers have been recently used for data serializing in large on-chip systems to alleviate the routing congestion and improve the routability. FPGAs have considerable potential for using the asynchronous serial transmission but they have serious challenges to use this technology. In this paper, we present a new FPGA architecture corresponding with a new routing algorithm to use the asynchronous data serializing technique in modern FPGAs. Experimental results show that allocated routing tracks and routing congestion can be reduced considerably (18.81% and 48.73%, respectively) by using the asynchronous data serializing without any performance degradation in cost of reasonable overhead in area and power consumption. The resulting improvements will increase for larger and more complex FPGAs.
VLSI physical design algorithms are generally nonpolynomial algorithms with very long runtime. In... more VLSI physical design algorithms are generally nonpolynomial algorithms with very long runtime. In this paper, we parallelize the Pathfinder global routing algorithm-a widely used FPGA routing algorithm-for running on multi-core systems to improve runtime of routing process. Our experimental results show that the runtime of proposed multi-threaded global routing reduces by 47.8% and 70.9% (on average) with 2 and 4 concurrent threads, respectively on a quad-core processor without any quality degradation.
In this paper, a mathematical solution for integrated buffer and Through-Silicon Via (TSV) planni... more In this paper, a mathematical solution for integrated buffer and Through-Silicon Via (TSV) planning in three-dimensional chips is presented in which the optimal location of both buffer and TSV of each net is determined simultaneously. In this method, twodimensional buffer planning formulation is extended to threedimensional era. Experimental results show that performance and probability of successful buffer/TSV insertion is increased considerably, especially for large and congested three-dimensional circuits.
Interconnect mis-prediction is a major problem in nano-scale design that may diminish the quality... more Interconnect mis-prediction is a major problem in nano-scale design that may diminish the quality of physical design algorithms or may even result in design divergence. In this paper, a new interconnect-planning methodology based on assume and enforce strategy is presented. In this methodology, some regions of the chip are planned to provide auxiliary routing resources and improve the interconnect delay of critical nets during the floor-placement process. Each of these wealthy regions is called a highway-on-chip. The location of highways and their resources are gradually determined during the hierarchical floor-placement process. Experimental results show that the performance, timing yield, predictability and power consumption of the attempted benchmarks are improved by 13.66%, 10.02%, 20.11%, and 6.83% on average. These improvements are obtained at the cost of about 7.82% runtime overhead and less than 0.8% wirelength growth.
Digital data production speeds up dramatically every day, and the need to store extensive data ri... more Digital data production speeds up dramatically every day, and the need to store extensive data rises consequently. Many storage media are used today, but only a few are capable of the required features in terms of high density, data duration, storage lifetime, and reliability. DNA-based digital data storage systems are one of the new and feature-rich media to store a massive amount of data in a very tiny volume with a strange lifetime. However, building dense and straightforward DNA storage comes with some challenges. Using manual methods to transfer and mix liquids containing DNA molecules makes this storage more error-prone. Moreover, the encoding method of digital data into DNA molecules is very crucial. This paper proposes a novel method for automatic and controllable DNA strand manipulation using a customized Digital Microfluidic Biochip (DMFB) corresponding to the CAD algorithm. Then, we offer a new approach to encoding the digital data into DNA molecules that helps error detection and correction in DNA storage while it brings efficient encoding density. Experimental results show that we can write 1.6 bits on each nucleotide with a 200-base strand which is a good density compared with other methods. In contrast, the encoding method is much simpler and easier to implement.
Digital microfluidic biochips (DMFBs) are revolutionary biomedical devices towards diagnostics an... more Digital microfluidic biochips (DMFBs) are revolutionary biomedical devices towards diagnostics and point-of-care applications; the chips provide the capability of performing wide ranges of biochemistry and laboratory procedures, offering various opportunities among which to mention are automation, miniaturization and cost-affordability of bioassays. There have been various digital microfluidic biochips architectures; the application-specific chips are mainly suited towards executing a predefined set of bioassays whereas the more flexible generalpurpose chips allow executing wide ranges of bioassays on the same architecture. Though more flexible in terms of performing various bioassays the general-purpose chips require more complicated designs compared with application-specific counterparts necessitating larger and more costly designs. This paper attempts to propose a general-purpose field-programmable pin-constrained DMFB design with improved characteristics in terms area-consumption, manufacturing cost and performance.
DNA computing is a new kind of computation for solving the complex problems with the huge degree ... more DNA computing is a new kind of computation for solving the complex problems with the huge degree of parallelism. Recently it is found that DNA-based logic systems can be useful in many of biomedical applications such as early cancer detection. DNA logic systems have been applied successfully to detect the risky patterns of nucleotide-based cancer biomarkers (microRNAs). Detection of real diseases requires the large-scale DNA-based logical systems. Therefore, large-scale DNA-based logic circuits is a crucial research topic. In this paper, an automatic design flow is proposed to facilitate the design, verification and physical implementation of multi-stage and large-scale DNA logic circuits. Digital Microfluidic Biochips (DMFB) have been used recently as a promising platform for efficient implementation of DNA-based computing systems and circuits. We used this technology as the physical platform for implementation of DNA-based circuits. Our experiments and implementations show the feasibility, accuracy, efficiency and simplicity of the proposed design flow. Final DNA reactions that are synthesized by the proposed design flow are verified and simulated with stochastic DNA-reaction simulators to prove the correctness of the proposed design flow. This design flow can open a new horizon for researchers and scientists to design, implement and evaluate the DNA-based logic systems.
The template attack is one of the most efficient attacks for exploiting the secret key. Template-... more The template attack is one of the most efficient attacks for exploiting the secret key. Template-based attack extracts a model forthe behavior of side channel information from a device which is similar to the target device and then uses this model to retrievethe correct key on the target victim device. Until now, many researchers have focused on improving the performance of templateattacks ,but recently, a few countermeasures have been proposed to protect the design against these attacks. On the other hand,researches show that regular countermeasures against these attacks are costly. Randomized shuffling in the time domain is knownas a cost-effective countermeasure against side-channel attacks that are widely used. In this article, we implemented an actualtemplate attack and proposed an efficient countermeasure against it.We focus on the time shifting method against template attack.The results show that template attack is very susceptible to this method. The performance of attack on...
Intelligent car navigation systems are planned to assist humans and route them automatically in t... more Intelligent car navigation systems are planned to assist humans and route them automatically in the roads with sufficient security and correctness. Landmark-based car navigation is a widely used technique in automotive and robot navigation. In this paper, we improved a wireless landmark-based car navigation (WLCN) algorithm to operate in multi-agent (MA) environments. The extended navigation algorithm allows the cars to overtake in uni-directional real roads. Overtaking is based on the information which the cars send to each other in the road. According to this information and using a related algorithm, cars traverse each other. Analysis of accuracy and efficiency in various states, real-time RISC-based embedded system especially for high speed movements in real roads show that, the cars are navigated easily and reliable in multi-agent environments and they can successfully do overtake. In addition to reliable navigating, calculation cost of the algorithm is acceptable for real worl...
Side-channel analysis methods can reveal the secret information of digital electronic systems by ... more Side-channel analysis methods can reveal the secret information of digital electronic systems by analyzing the dependency between the power consumption of implemented cryptographic algorithms and the secret data. Recent studies show that it is possible to gather information about power consumption from FPGAs without any physical access. High flexibilities of modern FPGAs cause that they are used for cloud accelerator in Platform as a Service (PaaS) system; however, new serious vulnerabilities emerged for these platforms. Although there are some reports about how switching activities from one region of FPGA affect other regions, details of this technique are not analyzed. In this paper, we analyzed the strength of this kind of attack and examined the impact of geometrical and electrical parameters of the victim/attacker modules on the efficiency of this attack. We utilized a Zynq-based Xilinx platform as the device under attack. Experimental results and analyses show that the distanc...
A B S T R A C T Nowadays, bulk of the designers prefer to outsource some parts of their design an... more A B S T R A C T Nowadays, bulk of the designers prefer to outsource some parts of their design and fabrication process to the third-part companies due to the reliability problems, manufacturing cost and time-to-market limitations. In this situation, there are a lot of opportunities for malicious alterations by the o-shore companies. In this paper, we proposed a new placement algorithm that hinders the hardware Trojan insertion or simplies the detection process in existence of Trojans. Experimental results show that the proposed placement improves the Trojan detectability of the attempted benchmarks against Trojan insertion more than 20% in reasonable cost in delay and wire length.
Fab-less business model in semiconductor industry has led to serious concerns about trustworthy h... more Fab-less business model in semiconductor industry has led to serious concerns about trustworthy hardware. In untrusted foundries and manufacturing companies, submitted layout may be analyzed and reverse engineered to steal the information of a design or insert malicious Trojans. Understanding the netlist topology is the ultimate goal of the reverse engineering process. In this paper, we propose a netlist encryption mechanism to hide the interconnect topology inside an IC. Moreover, new special standard cells (Wire Scrambling cells) are designed to play the role of netlist encryption. Furthermore, a design flow is proposed to insert the WS-cells inside the netlist with the aim of maximum obfuscation and minimum overhead. It is worth noting that this mechanism is fully automated with no need to detail information of the functionality and structure of the design. Our proposed mechanism is implemented in an academic physical design framework (EduCAD). Experimental results show that reverse engineering can be hindered considerably in cost of negligible overheads by 23% in area, 3.25% in delay and 14.5% in total wire length. Reverse engineering is evaluated by brute-force attack, and the learned information is 0% and the Hamming distance is approximately 50%.
A Digital Microfluidic Biochip (DMFB) offers a promising platform for medical diagnostics, DNA se... more A Digital Microfluidic Biochip (DMFB) offers a promising platform for medical diagnostics, DNA sequencing, Polymerase Chain Reaction (PCR), and drug discovery and development. Conventional Drug discovery procedures require timely and costly manned experiments with a high degree of human errors with no guarantee of success. On the other hand, DMFB can be a great solution for miniaturization, integration, automation, and cost reduction of drug discovery. DMFB can improve the parallelism of drug discovery procedures; since most procedures in drug discovery are concurrent and parallel, DMB can reduce the execution time of these bioassays. Therefore, there is a critical need to develop DMFBs to speed up the drug discovery applications and improve cost and error of these reactions. In this paper, a new architecture is used for drug discovery applications. The architecture is evaluated and compared with FPPC architecture. The experimental results prove that the new architecture is faster and cheaper than FPPC; it reduces all the important parameters such as total execution time, number of controlling pins, CAD algorithm execution time, and the area usage and its costs. There is an urgent need for collaboration between experts of drug discovery, microfluidic platform architecture and also machine learning to design a data-driven microfluidic architecture which improves the CAD algorithms by learning from prior knowledge.
Micro/Nanofluidic biochips are used to automate the clinical diagnosis, DNA sequencing, automated... more Micro/Nanofluidic biochips are used to automate the clinical diagnosis, DNA sequencing, automated drug discovery and real time bio-molecular recognition. One of attractive usages of biochips is Lab-on-chip (LOC). Lab-on-Chip technology is a promising replacement for biomedical and chemical apparatus. Two main types of microfluidic based biochips are used: continuous-flow based and digital microfluidic biochips (DMFB). In DMFBs, liquids, in the form of droplets, are controlled independently and concurrently over a two dimensional array of cells (or electrodes).Digital microfluidic biochips provide high ability to configure and fault tolerance. In this paper, a new architecture for DMFB with purpose of balancing among the parameters of flexibility, efficiency, cost, and completion time of biological experiments, is presented. In the new architecture, a FPGA-based structure is used, which increase flexibility and paralellizing assay operations. Experiments show that, the execution time of scheduling, routing, and simulation are improved in comparison with FPPC architecture about 2.54%, 18.76% and 12.52%, respectively in cost of 21% overhead in the number of controlling pins.
International Journal of Computer Theory and Engineering, 2017
Significant portion of digital design flow runtime is related to the physical design stages. Part... more Significant portion of digital design flow runtime is related to the physical design stages. Partitioning is a critical stage of physical design and its quality and runtime has considerable impact on physical design efficiency. In this paper, a new parallel partitioning algorithm is proposed and it is suitable for GPU system. In the proposed algorithm, coarsening phase of the partitioning is accelerated by parallelizing on GPU. Experimental results show that runtime can be improved up to 7x for attempted circuit with negligible quality degradation. Index Terms-GPU programming, multilevel partitioning, parallel algorithms, physical design. I. INTRODUCTION Integrated circuits complexity has been grown in last decades with exponential rate and it is predicted that this flow will be continued in future years [1], [2]. This exponential growth of modern circuits is an important challenge for computer-aided design tools because their runtime will be increased dramatically coping with this complexity growth [3], [4]. On the other hand, the gap between complexity growth and productivity of CAD tools (i.e. productivity gap) will be increased for new ultra-large systems such as system-on-chips and multi-core systems. Considerable portion of total design time is related to physical design stage. Physical design consists of some important steps such as partitioning, floor-planning, placement and routing. In Partitioning phase, design graph is partitioned to some sub-graphs to facilitate rest of algorithms. Floor-planning find location and shape of large blocks. Exact location and orientation of the standard cells are fixed in placement step and finally, the geometry of interconnects will be determined in routing stage. A bundle of physical design algorithms are NP-complete and NP-hard [5], [6]. Graph partitioning is a critical sub-stage of physical design. Quality and execution time of partitioning stage has considerable impact on total quality of design and total execution time of physical design flow. Therefore, we focused on parallelizing the graph partitioning stage to improve its runtime regarding to the partitioning quality. Many contributions are reported on parallelizing the CAD algorithms on multi-processor systems in the last years of 90's
Recent improvements in the bio-engineering area have composed wonderful opportunities to manipula... more Recent improvements in the bio-engineering area have composed wonderful opportunities to manipulate the bio-structures. Biochips are known as electronic platforms to decrease the experiment time and cost and improve the exibility and automatability of operations. Digital micro/nano uidic biochips can carry discrete droplets of experiment materials on the chip to perform the projected assays. In this paper, a new FPGA-inspired architecture is proposed for micro-uidic biochips in order to improve the con gurability and exibility of the biochip and also reduce the number of controlling pins. The simulation results show that in the proposed architecture, number of controlling pins is improved by 6.35x compared with the direct addressing method and the total experiment time is reduced by 34% compared with the eld-programmable pin-constrained method, improving con gurability and exibility.
The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012), 2012
Replacing the conventional interconnects with newer material is an effective solution for the ser... more Replacing the conventional interconnects with newer material is an effective solution for the serious problems of these interconnects, especially in FPGAs in which more than of 70% of area covered by interconnects. In this paper, using the Carbon Nanotube (CNT) interconnects in FPGAs is explored and a CNT/Metal hybrid routing architecture for large FPGAs is proposed. In the presented architecture, both CNT and metal wires are utilized such that global wires are routed by CNT and local nets are constructed by metal wires. Our experimental results show that this architecture improves critical delay, total wirelength, and total power consumption by 10.87%, 1.28%, and 4.60%, respectively of attempted benchmarks.
Modern integrated circuits consist of millions of standard cells and routing paths. In nano-scale... more Modern integrated circuits consist of millions of standard cells and routing paths. In nano-scale designs, mis-prediction is a dominant problem that may diminish the quality of physical design algorithms or even result in the disruption of the convergence of the design cycle. In this paper, a new planning methodology is presented in which a masterplan of the chip is constructed at the early levels of the physical design, preparing for the operation of the subsequent physical design stages. As a proof of concept study, the proposed planning design flow is applied to both wire planning and buffer resource planning, and the outcomes are compared against conventional contributions. Experimental results reveal considerable improvements in terms of performance, timing yield and buffer usage.
20th Iranian Conference on Electrical Engineering (ICEE2012), 2012
Automotive embedded systems are widely used in modern vehicles such as cars, aircrafts and so on.... more Automotive embedded systems are widely used in modern vehicles such as cars, aircrafts and so on. However, modeling and evaluation of these systems is very challenging because time-to-market is very short and vehicles use very different platforms with various sensors, operating systems and embedded software modules. In this paper, we propose a TrueTime-based networked automotive platform (TrueFlex) which enables modeling and simulation of processing units, operating system kernels, communication bus and sensors/actuators in realtime or non-realtime automotive systems. This platform is easily upgradeable and provides different abstraction levels for modeling of automotive embedded systems with very informative reports and graphs. This platform is implemented and evaluated in this paper to show its very useful capabilities for automotive electronic designers.
Asynchronous serial transceivers have been recently used for data serializing in large on-chip sy... more Asynchronous serial transceivers have been recently used for data serializing in large on-chip systems to alleviate the routing congestion and improve the routability. FPGAs have considerable potential for using the asynchronous serial transmission but they have serious challenges to use this technology. In this paper, we present a new FPGA architecture corresponding with a new routing algorithm to use the asynchronous data serializing technique in modern FPGAs. Experimental results show that allocated routing tracks and routing congestion can be reduced considerably (18.81% and 48.73%, respectively) by using the asynchronous data serializing without any performance degradation in cost of reasonable overhead in area and power consumption. The resulting improvements will increase for larger and more complex FPGAs.
VLSI physical design algorithms are generally nonpolynomial algorithms with very long runtime. In... more VLSI physical design algorithms are generally nonpolynomial algorithms with very long runtime. In this paper, we parallelize the Pathfinder global routing algorithm-a widely used FPGA routing algorithm-for running on multi-core systems to improve runtime of routing process. Our experimental results show that the runtime of proposed multi-threaded global routing reduces by 47.8% and 70.9% (on average) with 2 and 4 concurrent threads, respectively on a quad-core processor without any quality degradation.
In this paper, a mathematical solution for integrated buffer and Through-Silicon Via (TSV) planni... more In this paper, a mathematical solution for integrated buffer and Through-Silicon Via (TSV) planning in three-dimensional chips is presented in which the optimal location of both buffer and TSV of each net is determined simultaneously. In this method, twodimensional buffer planning formulation is extended to threedimensional era. Experimental results show that performance and probability of successful buffer/TSV insertion is increased considerably, especially for large and congested three-dimensional circuits.
Interconnect mis-prediction is a major problem in nano-scale design that may diminish the quality... more Interconnect mis-prediction is a major problem in nano-scale design that may diminish the quality of physical design algorithms or may even result in design divergence. In this paper, a new interconnect-planning methodology based on assume and enforce strategy is presented. In this methodology, some regions of the chip are planned to provide auxiliary routing resources and improve the interconnect delay of critical nets during the floor-placement process. Each of these wealthy regions is called a highway-on-chip. The location of highways and their resources are gradually determined during the hierarchical floor-placement process. Experimental results show that the performance, timing yield, predictability and power consumption of the attempted benchmarks are improved by 13.66%, 10.02%, 20.11%, and 6.83% on average. These improvements are obtained at the cost of about 7.82% runtime overhead and less than 0.8% wirelength growth.
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Papers by Ali Jahanian