Minimizing power dissipation is an important design requirement for both portable and non-portabl... more Minimizing power dissipation is an important design requirement for both portable and non-portable systems. In this work, we propose an architectural solution to the power problem that retains performance while reducing power. The technique, known as Pipeline Balancing (PLB), dynamically tunes the resources of a general purpose processor to the needs of the program by monitoring performance within each program. We analyze metrics for triggering PLB, and detail instruction queue design and energy savings based on an extension of the Alpha 21264 processor. Using a detailed simulator, we present component and full chip power and energy savings for single and multi-threaded execution. Results show an issue queue and execution unit power reduction of up to 23% and 13%, respectively, with an average performance loss of 1% to 2%.
ACM Transactions on Design Automation of Electronic Systems, 2002
We utilize Rent's rule as an empirical measure for efficient clustering and placement of circuits... more We utilize Rent's rule as an empirical measure for efficient clustering and placement of circuits in clustered Field Programmable Gate Arrays (FPGAs). We show that careful matching of resource availability and design complexity during the clustering and placement processes can contribute to spatial uniformity in the placed design, leading to overall device decongestion after routing. We present experimental results to show that appropriate logic depopulation during clustering can have a positive impact on the overall FPGA device area. Our clustering and placement techniques can improve the overall device routing area by as much as 62%, 35% on average, for the same array size, when compared to state-of-the-art FPGA clustering, placement, and routing tools. Power dissipation simulations using a typical buffered pass-transistor-based FPGA interconnect model are also presented. They show that our clustering and placement techniques can reduce the overall device power dissipation by approximately 13%.
Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's
... Standby Leakage Power Reduction in CMOS K's Ali Keshavarzi, Siva Narendra, Shekhar Borka... more ... Standby Leakage Power Reduction in CMOS K's Ali Keshavarzi, Siva Narendra, Shekhar Borkar, Charles Hawkins', Kaushik Roy* and Vivek De MicroComputer Research Labs, 'The University of New Mexico, and 'Purdue University Intel Corporation, Hillsboro, OR 97124, USA ...
Minimizing power dissipation is an important design requirement for both portable and non-portabl... more Minimizing power dissipation is an important design requirement for both portable and non-portable systems. In this work, we propose an architectural solution to the power problem that retains performance while reducing power. The technique, known as Pipeline Balancing (PLB), dynamically tunes the resources of a general purpose processor to the needs of the program by monitoring performance within each program. We analyze metrics for triggering PLB, and detail instruction queue design and energy savings based on an extension of the Alpha 21264 processor. Using a detailed simulator, we present component and full chip power and energy savings for single and multi-threaded execution. Results show an issue queue and execution unit power reduction of up to 23% and 13%, respectively, with an average performance loss of 1% to 2%.
ACM Transactions on Design Automation of Electronic Systems, 2002
We utilize Rent's rule as an empirical measure for efficient clustering and placement of circuits... more We utilize Rent's rule as an empirical measure for efficient clustering and placement of circuits in clustered Field Programmable Gate Arrays (FPGAs). We show that careful matching of resource availability and design complexity during the clustering and placement processes can contribute to spatial uniformity in the placed design, leading to overall device decongestion after routing. We present experimental results to show that appropriate logic depopulation during clustering can have a positive impact on the overall FPGA device area. Our clustering and placement techniques can improve the overall device routing area by as much as 62%, 35% on average, for the same array size, when compared to state-of-the-art FPGA clustering, placement, and routing tools. Power dissipation simulations using a typical buffered pass-transistor-based FPGA interconnect model are also presented. They show that our clustering and placement techniques can reduce the overall device power dissipation by approximately 13%.
Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's
... Standby Leakage Power Reduction in CMOS K's Ali Keshavarzi, Siva Narendra, Shekhar Borka... more ... Standby Leakage Power Reduction in CMOS K's Ali Keshavarzi, Siva Narendra, Shekhar Borkar, Charles Hawkins', Kaushik Roy* and Vivek De MicroComputer Research Labs, 'The University of New Mexico, and 'Purdue University Intel Corporation, Hillsboro, OR 97124, USA ...
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