By bringing industrial-grade robustness and reliability to Ethernet, Time Sensitive Networking (T... more By bringing industrial-grade robustness and reliability to Ethernet, Time Sensitive Networking (TSN) offers an IEEE standard communication technology that enables interoperability between standard-conformant industrial devices from any vendor. It also eliminates the need for physical separation of critical and non-critical communication networks, which allows a direct exchange of data between operation centers and companies, a concept at the heart of the Industrial Internet of Things (IIoT). This article describes creating an end-to-end TSN network using specialized PCI Express (PCIe) cards and two final Linux endpoints. For this purpose, the two primary standards of TSN, IEEE 802.1AS (regarding clock synchronization), and IEEE 802.1Qbv (regarding time scheduled traffic) have been implemented in Linux equipment as well as a configuration and monitoring system.
TSN (Time-Sensitive Networking) has replaced outdated Fieldbus and non-deterministic Ethernet in ... more TSN (Time-Sensitive Networking) has replaced outdated Fieldbus and non-deterministic Ethernet in the Industry 4.0. Field buses are not capable of providing neither connection for industry 4.0 IoT (Internet of Things) nor compatibility between different manufacturers. On the other hand, Ethernet is not able to ensure real-time. On the contrary, TSN guarantees real-time transmission, IoT and compatibility between devices. However, adapting to frequently changing needs makes TSN protocol evolve continuously. For this reason, devices for TSN analysis, such as PCs or not advanced frame analysis equipment are not able to process TSN packets at the speed that standard advances, discarding them as wrong frames. The integration of a System on Chip (SoC) that contains an FPGA (Field Programmable Gate Array) and a microcontroller, with capacity for reconfiguration and monitoring of the frames in the protocol, would be an ideal solution to this problem. This paper describes how to encapsulate T...
International journal of humanities and social sciences, 2007
Distributed wireless sensor network consist on several scattered nodes in a knowledge area. Those... more Distributed wireless sensor network consist on several scattered nodes in a knowledge area. Those sensors have as its only power supplies a pair of batteries that must let them live up to five years without substitution. That-s why it is necessary to develop some power aware algorithms that could save battery lifetime as much as possible. In this is document, a review of power aware design for sensor nodes is presented. As example of implementations, some resources and task management, communication, topology control and routing protocols are named.
Critical systems require zero recovery time when a failure occurs in a communications network. Th... more Critical systems require zero recovery time when a failure occurs in a communications network. The soon to be implemented standard IEC 62439-3 defines the only two protocols, parallel redundancy protocol and high-availability seamless redundancy, which fulfill this requirement and ensure no frame loss in the presence of an error. These protocols also provide a hot-plugging capability, which allows elements to be added to or removed from the network without interrupting communications and the operation of the plant. The electricity sector has adopted these for power utility automation in the recently published IEC 61850-90-4. The challenge is to obtain an efficient approach for use in electronic devices, capable of managing the characteristic duplicates, and circulating frames of these protocols, coupled with agile architectures capable of dealing with real-time processing requirements, fast switching times, high throughput, and deterministic behavior. The main contribution of this paper is the in-depth analysis it makes of network parameters imposed by the application of the protocols to power utility automation, and the proposition of a frame management system based on a segmented memory system that improves frame detecting time and uses the smallest memory required in order to resolve all the issues dealt with.
The aim of this work is to design a real-time adaptive and reusable image enhancement architectur... more The aim of this work is to design a real-time adaptive and reusable image enhancement architecture for video signals, based on a statistical processing of the video sequence. The VHDL hardware description language has been used in order to make possible a top-down design methodology. Generic design methodology has been followed by means of two features of the VHDL: global packages and generic pass. Image processing systems like this one require specific simulation tools in order to reduce the development time. A VHDL test bench has been designed specifically for image processing applications to facilitate the simulation process. It was necessary to define a new image file format with special characteristics for this purpose. A physical realization has been carried out on a FPGA to prove the validation of the design.
This article presents a series of hardware implementations of a general regression neural network... more This article presents a series of hardware implementations of a general regression neural network (GRNN) using FPGAs. The paper describes the study of this neural network using different fixed and floating point implementations. The implementation includes training as well as testing of the network. It is focused on precision loss and area and speed results of the resulting neural network
This paper presents a secured I2C (Inter-Integrated Circuit) protocol for Chip-to-Chip communicat... more This paper presents a secured I2C (Inter-Integrated Circuit) protocol for Chip-to-Chip communications. The well known AES-GCM cryptographic and authentication algorithm is used to secure this low speed serial communication protocol. This securization allows the use of this standard into applications where security is an issue and the computation resources are constrained. Both the hardware architecture and the protocol are presented.
IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society, 2013
The IEC62439-3: Industrial communication networks - High availability automation networks - Part ... more The IEC62439-3: Industrial communication networks - High availability automation networks - Part 3: Parallel Redundancy Protocol (PRP) and High-availability Seamless Redundancy (HSR), defines two protocols which provides zero time recovery against a failure in the network. The first edition of the standard was published in 2010, and two years after a second edition has been published in July 2012. There have been some improvements which explain this actualization and an amendment between versions. This paper presents the most remarkable improvements included, others susceptible of being included and a software prototype to be run in PCs and/or FPGAs which implements this new version of the protocols.
In this paper we present the design and implementation of a robust, marketable, general purpose a... more In this paper we present the design and implementation of a robust, marketable, general purpose and flexibly configurable device that offers three years of battery lifetime, GSM communications, local and/or remotely configurable behaviour, with wired and/or remote firmware-update facility and "one month before battery depletion" warning. It has been designed based upon WSN's power-aware techniques and empirical obtained results borne laboratory measurements out.
The node location problem in wireless networks has been a research interest in the last years. In... more The node location problem in wireless networks has been a research interest in the last years. In environments where GPS is not an option (e.g., for consumption reasons or because there is no direct link with the satellite constellation), the estimation of a node position using only RF signals is not a trivial task. Although some other systems have been proposed (ultrasonic signals, IR, etc.), these require additional hardware that is only useful for location purposes. According to this point, some algorithms have been proposed for providing sensible position estimations in the presence of distance errors. These methods normally require heavy computational processes to overcome the presence of these errors or easily degrade when the distance measurements have a certain magnitude. This paper describes an algorithm to compute the location of a node in the presence of severe distance estimation errors and analyzes its performance and computational cost. To make the implementation of this algorithm feasible in wireless sensor networks, different optimization techniques are proposed, in order to speed-up the location estimation of a node, without losing its estimating power.
The design of complex electronic circuits such as image processing circuits require new specific ... more The design of complex electronic circuits such as image processing circuits require new specific simulation and modelling tools, in order to reduce the development time. To simulate image-processing models described in VHDL an application specific test bench is needed. In this work a VHDL test bench was designed specifically for image-processing applications. It was necessary to define a new image file format with special characteristics to be used with VHDL and to be configurable to use in image applications with different specifications.
Computer Aided Design of Integrated Circuits and Systems Ieee Transactions on, May 1, 2006
In this paper, two designs for the decoder of the multifunction vehicle bus (MVB) are compared. T... more In this paper, two designs for the decoder of the multifunction vehicle bus (MVB) are compared. The first one follows a bottom-up methodology and the second one has been created in a top-down style. Although this latter methodology is more systematic and easy to automate, it results in a lower performance. In the case of the MVB decoder, the ratio of bottom-up performance to the top-down one ranges from 1.90 to 4.12, depending on the synthesis tool and the device. Selecting as reference the tool and field-programmable gate array (FPGA) that use the fewest logical elements, the bottom-up design can work 2.3 times faster than the top-down one, after two and three iterations for the physical implementation, respectively. In both cases, the circuit has been synthesized on a Virtex-E XCV3200E of Xilinx by Xilinx Synthesis Tool (XST), so that there has been no shortage of physical resources. Therefore, for a particular pair of synthesis tool and device, the final implementation is determined by the design style and not by a hard placement and routing in a hostile fabric. After synthesis, the top-down design was 23.37 % larger than the bottom-up design, so the results are not as poor as expected from a nonstructured design; however, this percentage, which is always positive, depends very strongly upon the particular synthesis tool and FPGA. In addition, both descriptions have been completely implemented in a similar CPU time (even the top-down one slightly more quickly, at the first attempt). So the top-down design style is a good candidate to produce circuits in a short time to market (in this case 28 % lower), although synthesis tools must be improved in order to increase the performance.
Ieee Transactions on Vehicular Technology, Nov 1, 2007
This paper presents the design of a network master device for the multifunction vehicle bus. An a... more This paper presents the design of a network master device for the multifunction vehicle bus. An analysis of the specifications for this bus administrator reveals that the functional design can be arranged in 14 operational blocks and in a special memory for communication data known as the traffic store. System-on-a-chip strategies have been adopted in order to cope with this great complexity. The architecture includes a standard on-chip bus, which is aimed at interconnecting all the modules as cores attached to it by an established interface. In this way, creation flow can be concurrent, and design for reuse is made easier. The entire architecture has been coded in SystemC not only for verification purposes but also for setting the intermediate point in the refinement process toward the register transfer-level design. After validating this executable description by simulation, the hardware/software partition has been performed following the codesign philosophy. Estimations about consumed silicon area, hardware response time, occupied program memory, and software execution time have been made in order to calculate a cost function for each functional block: the cost-performance difference. From these, an optimum hardware/software architecture has been obtained. As a result, the electronic platform for the master device has been generated on a field-programmable gate array. The final implementation contains a soft processor as the main component, a ROM, a RAM, some internal registers, and the Traffic Store.
This paper describes a clustering technique using Self Organizing Maps and a two-dimensional hist... more This paper describes a clustering technique using Self Organizing Maps and a two-dimensional histogram of the image. The twodimensional histogram is found using the pixel value and the mean in the neighborhood. This histogram is fed to a self organizing map that divides the histogram into regions. Carefully selecting the number of regions, a scheme that allows an optimum optical recognition of texts can be found. The algorithm is specially suited for optical recognition application where a very high degree of confidence is needed. As an example application, the algorithm has been tested in a voting application, where a high degree of precision is required. Furthermore, the algorithm can be extended to any other thresholding or clustering applications.
In this paper we present the design and implementation of a robust, marketable, general purpose a... more In this paper we present the design and implementation of a robust, marketable, general purpose and flexibly configurable device that offers three years of battery lifetime, GSM communications, local and/or remotely configurable behaviour, with wired and/or remote firmware-update facility and "one month before battery depletion" warning. It has been designed based upon WSN's power-aware techniques and empirical obtained results borne laboratory measurements out.
A novel cryptographic core (cryptocore) approach for secure communications is presented in this w... more A novel cryptographic core (cryptocore) approach for secure communications is presented in this work. It is an AES-Counter Mode core for System-on-Programmable-Devices that takes advantage from the flexibility of the reconfigurable devices. The proposed architecture is parameterizable, so it is easily scalable to fulfill different target area-speed trade-offs. This parametrization affects both the number of AES cipher block processors running in parallel and the implementation type. The crypto-core supports three AES cipher blocks implementations publicly available. The proposed architecture is analyzed with experimental results that show how the crypto-core eases and optimizes the secure communications implementation in different systems.
... and memory, but it must take into account that the tools and software stack of the ... the de... more ... and memory, but it must take into account that the tools and software stack of the ... the design of complex systems which allows very short time-to-market and facilitates custom device design ... In Section 2, the functionality of a basic BCU and the new generation of FLASH memory ...
By bringing industrial-grade robustness and reliability to Ethernet, Time Sensitive Networking (T... more By bringing industrial-grade robustness and reliability to Ethernet, Time Sensitive Networking (TSN) offers an IEEE standard communication technology that enables interoperability between standard-conformant industrial devices from any vendor. It also eliminates the need for physical separation of critical and non-critical communication networks, which allows a direct exchange of data between operation centers and companies, a concept at the heart of the Industrial Internet of Things (IIoT). This article describes creating an end-to-end TSN network using specialized PCI Express (PCIe) cards and two final Linux endpoints. For this purpose, the two primary standards of TSN, IEEE 802.1AS (regarding clock synchronization), and IEEE 802.1Qbv (regarding time scheduled traffic) have been implemented in Linux equipment as well as a configuration and monitoring system.
TSN (Time-Sensitive Networking) has replaced outdated Fieldbus and non-deterministic Ethernet in ... more TSN (Time-Sensitive Networking) has replaced outdated Fieldbus and non-deterministic Ethernet in the Industry 4.0. Field buses are not capable of providing neither connection for industry 4.0 IoT (Internet of Things) nor compatibility between different manufacturers. On the other hand, Ethernet is not able to ensure real-time. On the contrary, TSN guarantees real-time transmission, IoT and compatibility between devices. However, adapting to frequently changing needs makes TSN protocol evolve continuously. For this reason, devices for TSN analysis, such as PCs or not advanced frame analysis equipment are not able to process TSN packets at the speed that standard advances, discarding them as wrong frames. The integration of a System on Chip (SoC) that contains an FPGA (Field Programmable Gate Array) and a microcontroller, with capacity for reconfiguration and monitoring of the frames in the protocol, would be an ideal solution to this problem. This paper describes how to encapsulate T...
International journal of humanities and social sciences, 2007
Distributed wireless sensor network consist on several scattered nodes in a knowledge area. Those... more Distributed wireless sensor network consist on several scattered nodes in a knowledge area. Those sensors have as its only power supplies a pair of batteries that must let them live up to five years without substitution. That-s why it is necessary to develop some power aware algorithms that could save battery lifetime as much as possible. In this is document, a review of power aware design for sensor nodes is presented. As example of implementations, some resources and task management, communication, topology control and routing protocols are named.
Critical systems require zero recovery time when a failure occurs in a communications network. Th... more Critical systems require zero recovery time when a failure occurs in a communications network. The soon to be implemented standard IEC 62439-3 defines the only two protocols, parallel redundancy protocol and high-availability seamless redundancy, which fulfill this requirement and ensure no frame loss in the presence of an error. These protocols also provide a hot-plugging capability, which allows elements to be added to or removed from the network without interrupting communications and the operation of the plant. The electricity sector has adopted these for power utility automation in the recently published IEC 61850-90-4. The challenge is to obtain an efficient approach for use in electronic devices, capable of managing the characteristic duplicates, and circulating frames of these protocols, coupled with agile architectures capable of dealing with real-time processing requirements, fast switching times, high throughput, and deterministic behavior. The main contribution of this paper is the in-depth analysis it makes of network parameters imposed by the application of the protocols to power utility automation, and the proposition of a frame management system based on a segmented memory system that improves frame detecting time and uses the smallest memory required in order to resolve all the issues dealt with.
The aim of this work is to design a real-time adaptive and reusable image enhancement architectur... more The aim of this work is to design a real-time adaptive and reusable image enhancement architecture for video signals, based on a statistical processing of the video sequence. The VHDL hardware description language has been used in order to make possible a top-down design methodology. Generic design methodology has been followed by means of two features of the VHDL: global packages and generic pass. Image processing systems like this one require specific simulation tools in order to reduce the development time. A VHDL test bench has been designed specifically for image processing applications to facilitate the simulation process. It was necessary to define a new image file format with special characteristics for this purpose. A physical realization has been carried out on a FPGA to prove the validation of the design.
This article presents a series of hardware implementations of a general regression neural network... more This article presents a series of hardware implementations of a general regression neural network (GRNN) using FPGAs. The paper describes the study of this neural network using different fixed and floating point implementations. The implementation includes training as well as testing of the network. It is focused on precision loss and area and speed results of the resulting neural network
This paper presents a secured I2C (Inter-Integrated Circuit) protocol for Chip-to-Chip communicat... more This paper presents a secured I2C (Inter-Integrated Circuit) protocol for Chip-to-Chip communications. The well known AES-GCM cryptographic and authentication algorithm is used to secure this low speed serial communication protocol. This securization allows the use of this standard into applications where security is an issue and the computation resources are constrained. Both the hardware architecture and the protocol are presented.
IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society, 2013
The IEC62439-3: Industrial communication networks - High availability automation networks - Part ... more The IEC62439-3: Industrial communication networks - High availability automation networks - Part 3: Parallel Redundancy Protocol (PRP) and High-availability Seamless Redundancy (HSR), defines two protocols which provides zero time recovery against a failure in the network. The first edition of the standard was published in 2010, and two years after a second edition has been published in July 2012. There have been some improvements which explain this actualization and an amendment between versions. This paper presents the most remarkable improvements included, others susceptible of being included and a software prototype to be run in PCs and/or FPGAs which implements this new version of the protocols.
In this paper we present the design and implementation of a robust, marketable, general purpose a... more In this paper we present the design and implementation of a robust, marketable, general purpose and flexibly configurable device that offers three years of battery lifetime, GSM communications, local and/or remotely configurable behaviour, with wired and/or remote firmware-update facility and "one month before battery depletion" warning. It has been designed based upon WSN's power-aware techniques and empirical obtained results borne laboratory measurements out.
The node location problem in wireless networks has been a research interest in the last years. In... more The node location problem in wireless networks has been a research interest in the last years. In environments where GPS is not an option (e.g., for consumption reasons or because there is no direct link with the satellite constellation), the estimation of a node position using only RF signals is not a trivial task. Although some other systems have been proposed (ultrasonic signals, IR, etc.), these require additional hardware that is only useful for location purposes. According to this point, some algorithms have been proposed for providing sensible position estimations in the presence of distance errors. These methods normally require heavy computational processes to overcome the presence of these errors or easily degrade when the distance measurements have a certain magnitude. This paper describes an algorithm to compute the location of a node in the presence of severe distance estimation errors and analyzes its performance and computational cost. To make the implementation of this algorithm feasible in wireless sensor networks, different optimization techniques are proposed, in order to speed-up the location estimation of a node, without losing its estimating power.
The design of complex electronic circuits such as image processing circuits require new specific ... more The design of complex electronic circuits such as image processing circuits require new specific simulation and modelling tools, in order to reduce the development time. To simulate image-processing models described in VHDL an application specific test bench is needed. In this work a VHDL test bench was designed specifically for image-processing applications. It was necessary to define a new image file format with special characteristics to be used with VHDL and to be configurable to use in image applications with different specifications.
Computer Aided Design of Integrated Circuits and Systems Ieee Transactions on, May 1, 2006
In this paper, two designs for the decoder of the multifunction vehicle bus (MVB) are compared. T... more In this paper, two designs for the decoder of the multifunction vehicle bus (MVB) are compared. The first one follows a bottom-up methodology and the second one has been created in a top-down style. Although this latter methodology is more systematic and easy to automate, it results in a lower performance. In the case of the MVB decoder, the ratio of bottom-up performance to the top-down one ranges from 1.90 to 4.12, depending on the synthesis tool and the device. Selecting as reference the tool and field-programmable gate array (FPGA) that use the fewest logical elements, the bottom-up design can work 2.3 times faster than the top-down one, after two and three iterations for the physical implementation, respectively. In both cases, the circuit has been synthesized on a Virtex-E XCV3200E of Xilinx by Xilinx Synthesis Tool (XST), so that there has been no shortage of physical resources. Therefore, for a particular pair of synthesis tool and device, the final implementation is determined by the design style and not by a hard placement and routing in a hostile fabric. After synthesis, the top-down design was 23.37 % larger than the bottom-up design, so the results are not as poor as expected from a nonstructured design; however, this percentage, which is always positive, depends very strongly upon the particular synthesis tool and FPGA. In addition, both descriptions have been completely implemented in a similar CPU time (even the top-down one slightly more quickly, at the first attempt). So the top-down design style is a good candidate to produce circuits in a short time to market (in this case 28 % lower), although synthesis tools must be improved in order to increase the performance.
Ieee Transactions on Vehicular Technology, Nov 1, 2007
This paper presents the design of a network master device for the multifunction vehicle bus. An a... more This paper presents the design of a network master device for the multifunction vehicle bus. An analysis of the specifications for this bus administrator reveals that the functional design can be arranged in 14 operational blocks and in a special memory for communication data known as the traffic store. System-on-a-chip strategies have been adopted in order to cope with this great complexity. The architecture includes a standard on-chip bus, which is aimed at interconnecting all the modules as cores attached to it by an established interface. In this way, creation flow can be concurrent, and design for reuse is made easier. The entire architecture has been coded in SystemC not only for verification purposes but also for setting the intermediate point in the refinement process toward the register transfer-level design. After validating this executable description by simulation, the hardware/software partition has been performed following the codesign philosophy. Estimations about consumed silicon area, hardware response time, occupied program memory, and software execution time have been made in order to calculate a cost function for each functional block: the cost-performance difference. From these, an optimum hardware/software architecture has been obtained. As a result, the electronic platform for the master device has been generated on a field-programmable gate array. The final implementation contains a soft processor as the main component, a ROM, a RAM, some internal registers, and the Traffic Store.
This paper describes a clustering technique using Self Organizing Maps and a two-dimensional hist... more This paper describes a clustering technique using Self Organizing Maps and a two-dimensional histogram of the image. The twodimensional histogram is found using the pixel value and the mean in the neighborhood. This histogram is fed to a self organizing map that divides the histogram into regions. Carefully selecting the number of regions, a scheme that allows an optimum optical recognition of texts can be found. The algorithm is specially suited for optical recognition application where a very high degree of confidence is needed. As an example application, the algorithm has been tested in a voting application, where a high degree of precision is required. Furthermore, the algorithm can be extended to any other thresholding or clustering applications.
In this paper we present the design and implementation of a robust, marketable, general purpose a... more In this paper we present the design and implementation of a robust, marketable, general purpose and flexibly configurable device that offers three years of battery lifetime, GSM communications, local and/or remotely configurable behaviour, with wired and/or remote firmware-update facility and "one month before battery depletion" warning. It has been designed based upon WSN's power-aware techniques and empirical obtained results borne laboratory measurements out.
A novel cryptographic core (cryptocore) approach for secure communications is presented in this w... more A novel cryptographic core (cryptocore) approach for secure communications is presented in this work. It is an AES-Counter Mode core for System-on-Programmable-Devices that takes advantage from the flexibility of the reconfigurable devices. The proposed architecture is parameterizable, so it is easily scalable to fulfill different target area-speed trade-offs. This parametrization affects both the number of AES cipher block processors running in parallel and the implementation type. The crypto-core supports three AES cipher blocks implementations publicly available. The proposed architecture is analyzed with experimental results that show how the crypto-core eases and optimizes the secure communications implementation in different systems.
... and memory, but it must take into account that the tools and software stack of the ... the de... more ... and memory, but it must take into account that the tools and software stack of the ... the design of complex systems which allows very short time-to-market and facilitates custom device design ... In Section 2, the functionality of a basic BCU and the new generation of FLASH memory ...
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Papers by Aitzol Zuloaga