A. Hlawiczka

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James Elkins

School of the Art Institute of Chicago

David Seamon

Kansas State University

Aswani Kumar Cherukuri

VIT University

Fabio Cuzzolin

Oxford Brookes University

Monish Chatterjee

University of Dayton

Rigas Kotsakis

Aristotle University of Thessaloniki

José Francisco Pessanha

UERJ - Universidade do Estado do Rio de Janeiro / Rio de Janeiro State University

Rocco Langone

KU Leuven

Abdel Salam El-Koumy

Suez Canal University

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Papers by A. Hlawiczka

On detection of interconnect faults by a MISR compactor-unknown problems and new solutions

Skuteczny generator testów dla przesłuchów w połączeniach

On design of high speed tests pattern generators based on ring LFSRs

Electronics and Telecommunications Quarterly, 2008

Initialisation of BIST Circuits Based on Rule 60 Cellular Automata

IFAC Proceedings Volumes, 2000

A theory of initialising new type linear test pattern generators (TPGs) based on rule 60 Cellular... more A theory of initialising new type linear test pattern generators (TPGs) based on rule 60 Cellular Automata (register composed ofT-type flip-flops only) is developed in the paper. Two practical ways of setting an initial state of such registers are also shown. One of them is based on the use of external tester while another one is well suited to BIST applications. They both involve much less area overhead than hitherto employed TPG initialisation techniques, which require using either T-type flip-flops with set or reset inputs or T-type flip-flops equipped with scan mode.

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Integration of a Long Test Pattern Generator Composed of T-Type Flip-Flops into a Scan Path

IFAC Proceedings Volumes, 2003

A new structure of the fast and Iow-area test pattern generator (TPG) based on a long linear regi... more A new structure of the fast and Iow-area test pattern generator (TPG) based on a long linear register composed of T-type flip-flops that can be easily integrated with the scan path is proposed for a BIST in the paper. In addition, authors propose a testing method that is suitable for verifying correct functioning of both the scan-path and the new type TPGs incorporated in it.

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B08: A novel method of designing linear ring generators and compactors

IFAC Proceedings Volumes, 2004

The paper describes a method of designing ring registers that lack long feedback connections and ... more The paper describes a method of designing ring registers that lack long feedback connections and contain cells functioning as D or T flip-flops. The method consists on the transformation of any source primitive characteristic polynomial p(x) into its ring structural form, which makes possible to directly draw the related schematic diagram of the ring register to be developed. It is proposed to employ a technique that enables obtaining low fan-outs on the outputs of each cell of the ring register and a minimal number of layers of XOR gates (hence, minimal propagation times) between these cells. There is included a series of examples of designing of ring registers and there is proposed a new technique of defining the source characteristic polynomial based on the ring structure of a linear register.

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Low cost BIST for EDAC circuits

Proceedings Sixth Asian Test Symposium (ATS'97), 1997

An application of new idea of designing circular self-test path (CSTP) for EDAC circuit is given ... more An application of new idea of designing circular self-test path (CSTP) for EDAC circuit is given in the paper. The new BIST scheme called in the paper as a condensed circular self-test path (CCSTP=C/sup 2/STP) makes possible to reduce significantly the number of CBIST cells to a smaller value. We focus on the analysis of the state transition graph (STG) as a key to understand the state coverage, fault coverage, and zero aliasing of condensed circular BIST (CBIST) schemes. There are given two examples of C/sup 2/BIST design. Particularly, the simple example of C/sup 2/STP design for 4-bit errors detection and errors correction (EDAC) circuit indicates advantages of such BIST technique. On the basis of this example it is shown that the time and complexity of simulation process for C/sup 2/STP is smaller than those for CSTP configuration and the seek time of a solution giving quasi optimal effectiveness for C/sup 2/STP is considerably shorter.

Bist structure using multi-input shift register with initial value

Electronics Letters, 1987

Parallel signature analysers are very useful for compression of test response data for VLSI. In t... more Parallel signature analysers are very useful for compression of test response data for VLSI. In the letter the compression result is obtained from a signature of zeros alone or ones alone from a nonzero initial state, rather than from the traditional method of obtaining a nonzero signature from a zeroed MISR register. An algebraic description of such a signature analysis is given, realised by means of the external exclusive-OR-type MISR.

On the use of Ring LFSR based BIST for detection, identification and localization of static and dynamic faults in interconnects

Theoretical and Applied Informatics, 2009

In the paper a method of the fault detection, identification and localization by means of a ring ... more In the paper a method of the fault detection, identification and localization by means of a ring Linear Feedback Shift Register (LFSR) is presented. The properties of a ring LFSR and the method to design a ring LFSR based Built-In-Self Test (BIST) is also given. Practical examinations of a ring LFSR application for localization faults in 8-,16-,24- and 32-bit buses are presented. Some important observations regarding the types of characteristic polynomials used in ring LFSRs are also included. Finally, the obtained results are summarised.

Fault signature effectiveness of microcomputer address bus

Electronics Letters, 1984

The letter presents the analysis of the effectiveness of compact testing of a microcomputer addre... more

Dependable computing-EDCC-2: proceedings; Taormina Italy, October 2-4, 1996

... at Urbana Champaign USA Asia: Hideo Fujiwara Nara Institute of Science and Technology Japan P... more

VLSI Wafers and Boards Diagnostics Using Multisignature Analysis

Fault Detection & Reliability, 1987

Hybrid design of parallel signature analyzers

[1989] Proceedings of the 1st European Test Conference, 1989

ABSTRACT Parallel signature analyzers implemented as multiple-input linear-feedback shift registe... more ABSTRACT Parallel signature analyzers implemented as multiple-input linear-feedback shift registers (MISRs) are very useful for compressing test response data. The author presents a top-bottom exclusive (TBE) MISR which uses only ( t +1)/2 XOR gates, in its linear feedback instead of t XOR gates used in other types of MISRs. An algebraic analysis of the operation and certain analytical results regarding the detection capability of a TBE-type MISR are included

Comments on "Procedures for Eliminating Static and Dynamic Hazards in Test Generation

IEEE Transactions on Computers, 2000

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Parallel signature analyzers using hybrid design of their linear feedbacks

IEEE Transactions on Computers, 1992

Parallel signature analyzers implemented as multiple input linear feedback shifl registers (MISR)... more Parallel signature analyzers implemented as multiple input linear feedback shifl registers (MISR) are very useful in compressing test response data. There are now two kinds of multiple linear shift registers differentiated by the means of realization of the linear feedback. There are External Exclusive OR (EE) and Internal Exclusive OR (IE) type MISR's respectively. This paper presents a bottom-top Exclusive OR (BTE) type MISR and a top-bottom Exclusive OR (TBE) type MISR which use only ( t + 1)/2 XOR gates in its linear feedback instead of t xOR gates used in E E or I E type MISR An algebraic analysis of the operation and certain analytical results regarding the detection capability of a BTE MISR are included. Infirmities of certain BTE type MISR and TBE type MISR with a reducible characteristic polynomial have been made. The proof that the probability of error sequence aliasing on a single input of BTE or TBE type MISR, where a characteristic polynomial of degree n is reducible, asymptotically approaches a value greater or equal to 2-" is also given in the paper.

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Compression of Three-State Data Serial Streams by Means of a Parallel LFSR Signature Analyzer

IEEE Transactions on Computers, 2000

ABSTRACT In this paper drawbacks of the three-state data compressor in the form of the unit decod... more ABSTRACT In this paper drawbacks of the three-state data compressor in the form of the unit decoder 3/2—JK flip-flop are described. The main results of the paper are the algebraic operation model and the description of detection capability of a new three-state data stream compressor consisting of decoder 3/2 and a two-input shift register TISR. In particular, the properties of the unit decoder 3/2—TISR in detecting faults of the s-a-0, s- a-1, and s-a-HZ type are discussed. In this paper important aspects of the application of the new compressor are given. An example of the new compressor&#39;s performance scheme is also described. An additional result of this paper is the description of the operation model and the detection capability of the multiinput shift register MISR in which the most significant bit and other selected flip-flop output signals are fed back to the least significant bit positions via Exclusive-OR gates outside the flip-flops.

Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata

Proceedings of the Ninth Asian Test Symposium, 2000

ABSTRACT The paper proposes the approach of designing CA registers that work as quick pattern gen... more ABSTRACT The paper proposes the approach of designing CA registers that work as quick pattern generators. A new effective method of setting the initial state of such registers is presented. It is based on switching a n-cell CA register into a concatenation of p CdSR registers (Cellular Automata quasi Shift Register) each containing r cells and connected with characteristic polynomial x&#39;. The resultant characteristic polynomial of such concatenation is p(x)=xn. Such concatenation of p registers CASR is referred as PCASR. The paper proves the possibility of setting a PCASR to any initial state by n-bit input sequence without the need of switching flip-flops into the D flip-flop mode. Moreover, it has been proven that any input sequence would be repeated at the output of a n-cell PCASR after n-clock cycle delay. Finally an effective procedure of testing PCASR is proposed

Test Pattern Generator for Delay Faults

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, 2007

One of the recently proposed solutions to the problem generation of test pairs' patterns to targe... more One of the recently proposed solutions to the problem generation of test pairs' patterns to target delay faults is a Multiple Input Signature Register (MISR). The paper proposes a method to minimize control words and to modify the operation diagram of the Test Pattern Generator (TPG) aiming at achieving acceptable test times while ensuring a very high coverage of Path Delay Faults (PDF). Experimental results are presented, in which the method of test pairs for benchmarks of the International Symposium on Circuits and Systems in 1989 (ISCAS'89) has been employed . Benchmarks presented in ISCAS'89 are sequential circuits. These results confirm a high effectiveness of this method compared to other solutions.

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Concatenable cellular automata register design for built-in self-test

[1992] Proceedings The European Conference on Design Automation, 1992

ABSTRACT The paper describes the principles of concatenations of cellular automata based LFSRs (M... more ABSTRACT The paper describes the principles of concatenations of cellular automata based LFSRs (MISR). It proves some theorems and lemmas which show if a certain cellular automata based register has a reducible polynomial of the form xg(x) or (x+l)h(x). Further it answers the question how to find a minimal set of standard CAD system cells to permit the construction of various length and various primitive characteristic polynomial cellular automata based LFSRs (MISRs). The paper also lists many examples of d-bit sliced cellular automata register families which allow for the building of concatenations having primitive polynomials

A linear code-preserving signature analyzer COPMISR

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125), 1997

ABSTRACT In this paper for an arbitrary linear separable code the concept of a COde Preserving Mu... more ABSTRACT In this paper for an arbitrary linear separable code the concept of a COde Preserving Multi-Input Signature Register COPMISR is introduced. For a code with k control bits 2k2 different COPMISR&#39;s can be designed. The optimum COPMISR with a minimum number of XOR-gates can be chosen from this large set. By different examples it is shown how the newly introduced COPMISR can be simultaneously utilized for concurrent checking, testing and localization of an eventually erroneous component of the monitored system. Since parity codes, group-parity codes, duplication codes and Hamming codes are special linear separable codes the concept of the COPMISR has a wide range of applications in different areas of on-line error detection and BIST

On detection of interconnect faults by a MISR compactor-unknown problems and new solutions

Skuteczny generator testów dla przesłuchów w połączeniach

On design of high speed tests pattern generators based on ring LFSRs

Electronics and Telecommunications Quarterly, 2008

Initialisation of BIST Circuits Based on Rule 60 Cellular Automata

IFAC Proceedings Volumes, 2000

Download

Integration of a Long Test Pattern Generator Composed of T-Type Flip-Flops into a Scan Path

IFAC Proceedings Volumes, 2003

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B08: A novel method of designing linear ring generators and compactors

IFAC Proceedings Volumes, 2004