Papers by David Moro-Frias
2013 10th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE), 2013
2008 3rd International Design and Test Workshop, 2008
The systematic design of the first generation (CCI), second generation (CCII), and third generati... more The systematic design of the first generation (CCI), second generation (CCII), and third generation (CCIII) current conveyor is presented by combining three kinds of unity-gain cells (UGCs), namely: the voltage follower (VF), the current follower (CF) and the current mirror (CM). Furthermore, it is highlighted that the CCI(II)(III) can be designed by evolving a VF biased with ideal current sources,
International Journal of Circuit Theory and Applications, 2009
New nullor-based models are introduced to describe the behavior of the first generation current c... more New nullor-based models are introduced to describe the behavior of the first generation current conveyor (CCI), second generation current conveyor (CCII), third generation current conveyor (CCIII), their inverting equivalents (ICCI(II)(III)), and/or their multiple output topologies (MO(I)CCI(II)(III)). These nullor equivalents include only grounded resistors to improve the formulation of equations in symbolic nodal analysis. In this manner, it is highlighted the usefulness of the proposed models to calculate analytical expressions in MO(I)CCI(II)(III)-based analog circuits. Figure 1. Nullor equivalents: (a) CCI+; (b) CCI−; (c) ICCI+; (d) ICCI−; and (e) MOICCI.
IEICE Electronics Express, 2008
It is introduced a new genetic algorithm to synthesize the negative-type second generation curren... more It is introduced a new genetic algorithm to synthesize the negative-type second generation current conveyor (CCII-) by superimposing a voltage follower (VF) with a current follower (CF). First, the VF and CF are described by binary genes. Second, the gene CF is inverted, rigth-shifted and multiplied (AND operation) with the gene VF to verify that both genes can be superimposed to synthesize the CCII-. Finally, some synthesized CCII-s are presented which electrical characteristics are measured using HSPICE and standard CMOS technology of 0.35 µm.
Circuits, Systems, and Signal Processing, 2014
ABSTRACT A novel current-mode Winner-Take-All (WTA) topology is presented in this paper. The dyna... more ABSTRACT A novel current-mode Winner-Take-All (WTA) topology is presented in this paper. The dynamic response of the circuit is improved by lowering the voltage swing required at the input nodes to turn on the winning cell. The WTA was designed and fabricated in 0.13 \(\upmu \) m CMOS technology with 2.5 V single supply voltage. Experimental results show an at least 26 % reduction in response time, as well as a reduction in the maximum output current error, when compared to other widely used current-mode topologies, with comparable bandwidth, area, and power consumption. The area of the proposed circuit is 47 \(\times \) 41 \(\upmu \mathrm{m}^{2}\) and it consumes 87 \(\upmu \) W per unit cell. The measured maximum output current error was 4.8 \(\upmu \) A, and a resolution of 1.85 \(\upmu \) A was obtained. The capability of the WTA to rectify signals was also experimentally demonstrated.
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Papers by David Moro-Frias