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Chi Tsui

Hong Kong University of Science and Technology, Department of Electronic and Computer Engineering, Faculty Member

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Universidad Nacional del Sur

Universitat de València

American University in Cairo

Kansas State University

National Institute of Technology, Calicut

Oxford Brookes University

Roshan Chitrakar

Nepal College of Information Technology

Graduate Center of the City University of New York

Prof.Dr. İbrahim USLU

Gazi University

Kenneth Vecchio

University of California, San Diego

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Papers by Chi Tsui

A VLSI architecture of a K-best lattice decoding algorithm for MIMO channels

Abstract Lattice decoding algorithms have been proposed for implementing the maximum likelihood d... more Abstract Lattice decoding algorithms have been proposed for implementing the maximum likelihood detector (MLD), which is the optimal receiver for multiple-input multiple-output (MIMO) channels. However the computational complexity of direct implementation of the lattice decoding algorithm is high and the throughput is variable. In this work, a K-best algorithm is proposed to implement the lattice decoding. It is computational inexpensive and has fixed throughput. It can be easily implemented in a pipelined fashion and has similar ...

Reducing power consumption of turbo code decoder using adaptive iteration with variable supply voltage

Turbo code becomes popular for the next generation wireless communication systems because of its ... more Turbo code becomes popular for the next generation wireless communication systems because of its remarkable coding performance. One of the problem for decoding turbo code in the receiver is the complexity and the high power consumption since multiple iterations of Soft Output Viterbi Algorithm (SOVA) have to be carried out to decode a data frame. In this paper, we address the issues of reducing the complexity and power consumption of turbo code decoder. An approach using cyclic redundancy checking (CRC) to adaptively terminate the SOVA iteration of each frame is presented. This results in system that has variable workload of which the amount of computation required for each data frame is different. Dynamic voltage scaling is then used to further reduce the power consumption. However, since the workload is not yet known at the time when the data is being decoded, optimum voltage assignment is not feasible. In this work, we propose two heuristic algorithms to assign supply voltage for different decoding iterations. Simulation results show that significant reduction of power consumption is achieved comparing with system using fixed supply voltage.

A low complexity architecture of the V-BLAST system

The V-BLAST architecture has been proposed as an extremely spectral efficient tool for wireless c... more The V-BLAST architecture has been proposed as an extremely spectral efficient tool for wireless communications. However, owing to the intensive computation involved, it may be difficult to implement this architecture for high data rate communication system. We propose the replacement of the optimal decoding order by a suboptimal one and the utilization of the Gram-Schmitt orthogonalization (GSO) to substitute the

Gate-level power estimation using tagged probabilistic simulation

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1998

In this paper, we present a probabilistic simulation technique to estimate the power consumption ... more In this paper, we present a probabilistic simulation technique to estimate the power consumption of a CMOS circuit under a general delay model. This technique is based on the notion of a tagged (probability) waveform, which models the set of all possible events at the output of each circuit node. Tagged waveforms are obtained by partitioning the logic waveform space of a circuit node according to the initial and final values of each logic waveform and compacting all logic waveforms in each partition by a single tagged waveform. To improve the efficiency of tagged probabilistic simulation, only tagged waveforms at the circuit inputs are exactly computed. The tagged waveforms of the remaining nodes are computed using a compositional scheme that propagates the tagged waveforms from circuit inputs to circuit outputs. We obtain significant speed up over explicit simulation methods with an average error of only 6%. This also represents a factor of 2-32 improvement in accuracy of power estimates over previous probabilistic simulation approaches.

Power estimation methods for sequential logic circuits

IEEE Transactions on Very Large Scale Integration Systems, 1995

Exact and approximate methods for calculating signal and transition probabilities in FSMs

In this paper, we consider the problem of calculating the signal and transition probabilitiesof t... more In this paper, we consider the problem of calculating the signal and transition probabilitiesof the internal nodes of the combinational logic part of a finite state machine(FSM). Given the state transition graph (STG) of the FSM, we first calculate the stateprobabilities by iteratively solving the Chapman-Kolmogorov equations. Using theseprobabilities, we then calculate the exact signal and transition probabilities by an

Power efficient technology decomposition and mapping under an extended power consumption model

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1994

We propose a new power consumption model that accounts for the power consumption at the internal ... more We propose a new power consumption model that accounts for the power consumption at the internal nodes of a CMOS gate. Next, we address the problem of minimizing the average power consumption during the technology dependent phase of logic synthesis. Our approach consists of two steps. In the first step, we generate a NAND decomposition of an optimized Boolean network such that the sum of average switching rates for all nodes in the network is minimum. In the second step, we perform a power efficient technology mapping that finds a minimal power mapping for given timing constraints (subject to the unknown load problem)

Technology decomposition and mapping targeting low power dissipation

... tions, quasi-linear ~unctions, for which Huffman's algo-rithm produces optimal trees und... more

Lower Power Architecture Design and Compilation Techniques for High-Performance Processors

Reducing switching activity would significantly reduce power consumption of a processor chip. In ... more

Improving the efficiency of power simulators by input vector compaction

Accurate power estimation is essential for low power digital CMOS circuit design. Power dissipati... more Accurate power estimation is essential for low power digital CMOS circuit design. Power dissipation is input pattern dependent. To obtain an accurate power estimate, a large input vector set must be used which leads to very long simulation time. One solution is to generate a compact vector set that is representative of the original input vector set and can be simulated in a reasonable time. In this paper, we propose an input vector compaction technique that preserves the statistical properties of the original sequence. Experimental results show that a compaction ratio of 100X is achieved with less than 2% average error in the power estimates.

Saving Power in the Control Path of Embedded Processors

IEEE Design & Test of Computers, 1994

... I CHING-LONG SU CHI-YING TSUl ALVIN M. DESPAIN University of Southern California ... We const... more

Low-power state assignment targeting two- and multilevel logic implementations

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1998

The problem of minimizing power consumption during the state encoding of a finite-state machine i... more The problem of minimizing power consumption during the state encoding of a finite-state machine is addressed. A new power cost model for state encoding is proposed, and encoding techniques that minimize this power cost for two-and multilevel logic implementations are described. These techniques are compared with those that minimize area or the switching activity at the present state bits. Experimental results show significant improvements. computer systems. His research group builds experimental software and hardware systems including compilers, simulators, design tools, custom VLSI processors, and multiprocessor systems. The goal is to determine principles for the design of high-performance computer systems. His research interests include computer architecture, multiprocessor systems, logic programming, quantum computation, and design automation.

Efficient estimation of dynamic power consumption under a real delay model

... Delay Model* Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain Department of Electrical Enginee... more

Power Estimation for Sequential Logic Circuits

Recently developed methods for power estimation have primarily focused on combinationallogic. In ... more Recently developed methods for power estimation have primarily focused on combinationallogic. In this paper, we present a framework for the efficient and accurate estimation of averagepower dissipation in sequential circuits.Switching activity is the primary cause of power dissipation in CMOS circuits. Accurateswitching activity estimation for sequential circuits is considerably more difficult than that forcombinational circuits, because the probability of the

Low power state assignment targeting two-and multi-level logic implementations

The problem of minimizing power consumption during the state encoding of a finite-state machine i... more The problem of minimizing power consumption during the state encoding of a finite-state machine is addressed. A new power cost model for state encoding is proposed, and encoding techniques that minimize this power cost for two-and multilevel logic implementations are described. These techniques are compared with those that minimize area or the switching activity at the present state bits. Experimental results show significant improvements. computer systems. His research group builds experimental software and hardware systems including compilers, simulators, design tools, custom VLSI processors, and multiprocessor systems. The goal is to determine principles for the design of high-performance computer systems. His research interests include computer architecture, multiprocessor systems, logic programming, quantum computation, and design automation.

Low power architecture design and compilation techniques for high-performance processors

Reducing switching activity would significantly reduce power consumption of a processor chip. In ... more

An Energy Efficient Layered Decoding Architecture for LDPC Decoder

Low-density parity-check (LDPC) decoder requires large amount of memory access which leads to hig... more Low-density parity-check (LDPC) decoder requires large amount of memory access which leads to high energy consumption. To reduce the energy consumption of the LDPC decoder, memory-bypassing scheme has been proposed for the layered decoding architecture which reduces the amount of access to the memory storing the soft posterior reliability values. In this work, we present a scheme that achieves the optimal reduction of memory access for the memory bypassing scheme. The amount of achievable memory bypassing depends on the decoding order of the layers. We formulate the problem of finding the optimal decoding order and propose algorithm to obtain the optimal solution. We also present the corresponding architecture which combines some of memory components and results in reduction of memory area. The proposed decoder was implemented in TSMC 0.18 m CMOS process. Experimental results show that for a LDPC decoder targeting IEEE 802.11n specification, the amount of memory access values can be reduced by 12.9-19.3% compared with the state-of-the-art design. At the same time, 95.6%-100% hardware utilization rate is achieved.

A VLSI architecture of a K-best lattice decoding algorithm for MIMO channels

Abstract Lattice decoding algorithms have been proposed for implementing the maximum likelihood d... more Abstract Lattice decoding algorithms have been proposed for implementing the maximum likelihood detector (MLD), which is the optimal receiver for multiple-input multiple-output (MIMO) channels. However the computational complexity of direct implementation of the lattice decoding algorithm is high and the throughput is variable. In this work, a K-best algorithm is proposed to implement the lattice decoding. It is computational inexpensive and has fixed throughput. It can be easily implemented in a pipelined fashion and has similar ...

Reducing power consumption of turbo code decoder using adaptive iteration with variable supply voltage

Turbo code becomes popular for the next generation wireless communication systems because of its ... more Turbo code becomes popular for the next generation wireless communication systems because of its remarkable coding performance. One of the problem for decoding turbo code in the receiver is the complexity and the high power consumption since multiple iterations of Soft Output Viterbi Algorithm (SOVA) have to be carried out to decode a data frame. In this paper, we address the issues of reducing the complexity and power consumption of turbo code decoder. An approach using cyclic redundancy checking (CRC) to adaptively terminate the SOVA iteration of each frame is presented. This results in system that has variable workload of which the amount of computation required for each data frame is different. Dynamic voltage scaling is then used to further reduce the power consumption. However, since the workload is not yet known at the time when the data is being decoded, optimum voltage assignment is not feasible. In this work, we propose two heuristic algorithms to assign supply voltage for different decoding iterations. Simulation results show that significant reduction of power consumption is achieved comparing with system using fixed supply voltage.

A low complexity architecture of the V-BLAST system

The V-BLAST architecture has been proposed as an extremely spectral efficient tool for wireless c... more The V-BLAST architecture has been proposed as an extremely spectral efficient tool for wireless communications. However, owing to the intensive computation involved, it may be difficult to implement this architecture for high data rate communication system. We propose the replacement of the optimal decoding order by a suboptimal one and the utilization of the Gram-Schmitt orthogonalization (GSO) to substitute the

Gate-level power estimation using tagged probabilistic simulation

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1998

In this paper, we present a probabilistic simulation technique to estimate the power consumption ... more In this paper, we present a probabilistic simulation technique to estimate the power consumption of a CMOS circuit under a general delay model. This technique is based on the notion of a tagged (probability) waveform, which models the set of all possible events at the output of each circuit node. Tagged waveforms are obtained by partitioning the logic waveform space of a circuit node according to the initial and final values of each logic waveform and compacting all logic waveforms in each partition by a single tagged waveform. To improve the efficiency of tagged probabilistic simulation, only tagged waveforms at the circuit inputs are exactly computed. The tagged waveforms of the remaining nodes are computed using a compositional scheme that propagates the tagged waveforms from circuit inputs to circuit outputs. We obtain significant speed up over explicit simulation methods with an average error of only 6%. This also represents a factor of 2-32 improvement in accuracy of power estimates over previous probabilistic simulation approaches.

Power estimation methods for sequential logic circuits

IEEE Transactions on Very Large Scale Integration Systems, 1995

Exact and approximate methods for calculating signal and transition probabilities in FSMs

In this paper, we consider the problem of calculating the signal and transition probabilitiesof t... more In this paper, we consider the problem of calculating the signal and transition probabilitiesof the internal nodes of the combinational logic part of a finite state machine(FSM). Given the state transition graph (STG) of the FSM, we first calculate the stateprobabilities by iteratively solving the Chapman-Kolmogorov equations. Using theseprobabilities, we then calculate the exact signal and transition probabilities by an

Power efficient technology decomposition and mapping under an extended power consumption model

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1994

We propose a new power consumption model that accounts for the power consumption at the internal ... more We propose a new power consumption model that accounts for the power consumption at the internal nodes of a CMOS gate. Next, we address the problem of minimizing the average power consumption during the technology dependent phase of logic synthesis. Our approach consists of two steps. In the first step, we generate a NAND decomposition of an optimized Boolean network such that the sum of average switching rates for all nodes in the network is minimum. In the second step, we perform a power efficient technology mapping that finds a minimal power mapping for given timing constraints (subject to the unknown load problem)

Technology decomposition and mapping targeting low power dissipation

... tions, quasi-linear ~unctions, for which Huffman's algo-rithm produces optimal trees und... more

Lower Power Architecture Design and Compilation Techniques for High-Performance Processors

Reducing switching activity would significantly reduce power consumption of a processor chip. In ... more

Improving the efficiency of power simulators by input vector compaction

Accurate power estimation is essential for low power digital CMOS circuit design. Power dissipati... more Accurate power estimation is essential for low power digital CMOS circuit design. Power dissipation is input pattern dependent. To obtain an accurate power estimate, a large input vector set must be used which leads to very long simulation time. One solution is to generate a compact vector set that is representative of the original input vector set and can be simulated in a reasonable time. In this paper, we propose an input vector compaction technique that preserves the statistical properties of the original sequence. Experimental results show that a compaction ratio of 100X is achieved with less than 2% average error in the power estimates.

Saving Power in the Control Path of Embedded Processors

IEEE Design & Test of Computers, 1994

... I CHING-LONG SU CHI-YING TSUl ALVIN M. DESPAIN University of Southern California ... We const... more

Low-power state assignment targeting two- and multilevel logic implementations

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1998

The problem of minimizing power consumption during the state encoding of a finite-state machine i... more The problem of minimizing power consumption during the state encoding of a finite-state machine is addressed. A new power cost model for state encoding is proposed, and encoding techniques that minimize this power cost for two-and multilevel logic implementations are described. These techniques are compared with those that minimize area or the switching activity at the present state bits. Experimental results show significant improvements. computer systems. His research group builds experimental software and hardware systems including compilers, simulators, design tools, custom VLSI processors, and multiprocessor systems. The goal is to determine principles for the design of high-performance computer systems. His research interests include computer architecture, multiprocessor systems, logic programming, quantum computation, and design automation.

Efficient estimation of dynamic power consumption under a real delay model

... Delay Model* Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain Department of Electrical Enginee... more

Power Estimation for Sequential Logic Circuits

Recently developed methods for power estimation have primarily focused on combinationallogic. In ... more Recently developed methods for power estimation have primarily focused on combinationallogic. In this paper, we present a framework for the efficient and accurate estimation of averagepower dissipation in sequential circuits.Switching activity is the primary cause of power dissipation in CMOS circuits. Accurateswitching activity estimation for sequential circuits is considerably more difficult than that forcombinational circuits, because the probability of the

Low power state assignment targeting two-and multi-level logic implementations

The problem of minimizing power consumption during the state encoding of a finite-state machine i... more The problem of minimizing power consumption during the state encoding of a finite-state machine is addressed. A new power cost model for state encoding is proposed, and encoding techniques that minimize this power cost for two-and multilevel logic implementations are described. These techniques are compared with those that minimize area or the switching activity at the present state bits. Experimental results show significant improvements. computer systems. His research group builds experimental software and hardware systems including compilers, simulators, design tools, custom VLSI processors, and multiprocessor systems. The goal is to determine principles for the design of high-performance computer systems. His research interests include computer architecture, multiprocessor systems, logic programming, quantum computation, and design automation.

Low power architecture design and compilation techniques for high-performance processors

Reducing switching activity would significantly reduce power consumption of a processor chip. In ... more

An Energy Efficient Layered Decoding Architecture for LDPC Decoder

Low-density parity-check (LDPC) decoder requires large amount of memory access which leads to hig... more Low-density parity-check (LDPC) decoder requires large amount of memory access which leads to high energy consumption. To reduce the energy consumption of the LDPC decoder, memory-bypassing scheme has been proposed for the layered decoding architecture which reduces the amount of access to the memory storing the soft posterior reliability values. In this work, we present a scheme that achieves the optimal reduction of memory access for the memory bypassing scheme. The amount of achievable memory bypassing depends on the decoding order of the layers. We formulate the problem of finding the optimal decoding order and propose algorithm to obtain the optimal solution. We also present the corresponding architecture which combines some of memory components and results in reduction of memory area. The proposed decoder was implemented in TSMC 0.18 m CMOS process. Experimental results show that for a LDPC decoder targeting IEEE 802.11n specification, the amount of memory access values can be reduced by 12.9-19.3% compared with the state-of-the-art design. At the same time, 95.6%-100% hardware utilization rate is achieved.