intel

121 Articles

A square red circuit board is shown on a black workbench. The circuit board houses two large chips in the upper left corner, each with a large heat sink attached.

Just How Bad Was The Intel IAPX432?

May 25, 2026 by 38 Comments

Processor design over the last few decades has moved toward RISC processors that aim to implement a few simple operations very efficiently. For a while, though, the trend was toward ever-more-complex CISC designs that let programmers implement complex behaviors using as few instructions as possible. Few processors took this approach further than the Intel iAPX432. This hyper-CISC processor was a commercial failure, largely due to its notoriously poor performance, but [MarkTheQuasiEngineer]’s benchmark suggests that this notoriety wasn’t totally deserved.

The first step before running a benchmark was to build a computer around the processor. The iAPX432 was implemented in three chips, two of which acted as the general data processor (GDP), and one of which handled input and output. [Mark] built an SBC (design and code here) that houses the two GDP chips and an FPGA for I/O. The 432 did have a well-deserved reputation for efficiently turning electricity into heat, and the original voltage regulator failed rather quickly.

The 432 was designed to use machine code which was almost a high-level language, with built-in object-oriented programming. It had over 200 operators, some of which implemented complex object-oriented operations, and a wide variety of data types, but it had no directly-accessible general-purpose registers. In addition to the lack of registers, it also had a very complex addressing system, allowing both direct and indirect addressing. For better performance, [Mark] used direct addressing.

For the benchmark, [Mark] implemented the Spigot algorithm to calculate the value of Pi. The results were somewhat surprising: calculating 2048 digits, it beat his previous retro-processor benchmarks; an Intel 8086 running the same algorithm took 2.5 times as long. Based on the results of this hand-written code, [Mark] speculates that the 432’s poor performance had more to do with poor compiler optimization than with the fundamental design.

We’ve covered some of the history of this troubled chip before. For a similarly ambitious but ill-fated Intel project, check out the history of Itanium.

Itanium: The Great X86 Replacement That Never Was

April 21, 2026 by 35 Comments

Itanium was once meant to be the next step in computing, to compete with the likes of IBM, Sun and DEC, but also for Intel to have an architecture that couldn’t be taken from it, as the PC was from IBM by its clones. Today, however, Itanium is a relic of the past. [Asianometry] tells us the story of Itanium.

By the ’90s, servers were an established market dominated by RISC architectures and Unix-like operating systems. Intel wanted to compete in this market, due in part to worries of losing control over x86. So, when Hewlett Packard came to Intel in late ’93, Intel eventually agreed to collaborate on a new project in EPIC (Explicitly Parallel Instruction Computing).
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Hackaday Links: March 8, 2026

March 8, 2026 by 8 Comments

As pointed out by Tom’s Hardware, it’s been 26 years since the introduction of the gigahertz desktop CPU. AMD beat Intel to the punch by dropping the 1 GHz Athlon chip on March 6th of 2000, and partnered with Compaq and Gateway (remember them?) to deliver pre-built machines featuring the speedy silicon just a week later. The archived press release announcing the availability of the chip makes for some interesting reading: AMD compares the accomplishment with Chuck Yeager breaking the sound barrier, and mentions a retail price of $1,299 for the CPU when purchased in 1,000 unit quantities. In response Intel “launched” their 1 GHz Pentium III chip two days later for $990, but supply problems kept it out of customer’s hands for most of the year.

Speaking of breaking a barrier, Mobile World Congress took place this week in Barcelona, where TechCrunch reports there was considerable interest in developing a sub-$50 smartphone. The GSM Association’s Handset Affordability Coalition is working with major telecom carriers in Africa and as of yet unnamed hardware partners to develop the low-cost 4G device with the hopes of bringing an additional 20 million people online. While the goal is worthy enough, industry insiders have pointed out that the skyrocketing cost of memory will make it particularly challenging to meet the group’s aspirational price point.

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The Intel 8087 And Conditional Microcode Tests

January 11, 2026 by 19 Comments

Continuing his reverse-engineering of the Intel 8087, [Ken Shirriff] covers the conditional tests that are implemented in the microcode of this floating point processing unit (FPU). This microcode contains the details on how to perform the many types of specialized instructions, like cos and arctan, all of which decode into many microcode ops. These micro ops are executed by the microcode engine, which [Ken] will cover in more detail in an upcoming article, but which is effectively its own CPU.

Conditional instructions are implemented in hardware, integrating the states of various functional blocks across the die, ranging from the instruction decoder to a register. Here, the evaluation is performed as close as possible to the source of said parameter to save on wiring.

Implementing this circuitry are multiplexers, with an example shown in the top die shot image. Depending on the local conditions, any of four pass transistors is energized, passing through that input. Not shown in the die shot image are the inverters or buffers that are required with the use of pass transistors to amplify the signal, since pass transistors do not provide that feature.

Despite how firmly obsolete the 8087 is today, it still provides an amazing learning opportunity for anyone interested in ASIC design, which is why it’s so great that [Ken] and his fellow reverse-engineering enthusiasts keep plugging away at recovering all this knowledge.

Benchmarking Chinese CPUs

November 26, 2025 by 25 Comments

When it comes to PCs, Westerners are most most familiar with x86/x64 processors from Intel and AMD, with Apple Silicon taking up a significant market share, too. However, in China, a relatively new CPU architecture is on the rise. A fabless semiconductor company called Loongson has been producing chips with its LoongArch architecture since 2021. These chips remain rare outside China, but some in the West have been benchmarking them.

[Daniel Lemire] has recently blogged about the performance of the Loongson 3A6000, which debuted in late 2023. The chip was put through a range of simple benchmarking tests, involving float processing and string transcoding operations. [Daniel] compared it to the Intel Xeon Gold 6338 from 2021, noting the Intel chip pretty much performed better across the board. No surprise given its extra clock rate. Meanwhile, the gang over at [Chips and Cheese] ran even more exhaustive tests on the same chip last year. The Loongson was put through typical tasks like  compressing archives and encoding video. The outlet came to the conclusion that the chip was a little weaker than older CPUs like AMD’s Zen 2 line and Intel’s 10th generation Core chips. It’s also limited as a four-core chip compared to modern Intel and AMD lines that often start at 6 cores as a minimum.

If you find yourself interested in Loongson’s product, don’t get too excited. They’re not exactly easy to lay your hands on outside of China, and even the company’s own website is difficult to access from beyond those shores. You might try reaching out to Loongson-oriented online communities if you seek such hardware.

Different CPU architectures have perhaps never been more relevant, particularly as we see the x86 stalwarts doing battle with the rise of desktop and laptop ARM processors. If you’ve found something interesting regarding another obscure kind of CPU, don’t hesitate to let the tipsline know!

Unusual Circuits In The Intel 386’s Standard Cell Logic

November 25, 2025 by 7 Comments

Intel’s 386 CPU is notable for being its first x86 CPU to use so-called standard cell logic, which swapped the taping out of individual transistors with wiring up standardized functional blocks. This way you only have to define specific gate types, latches and so on, after which a description of these blocks can be parsed and assembled by a computer into elements of a functioning application-specific integrated circuit (ASIC). This is standard procedure today with register-transfer level (RTL) descriptions being placed and routed for either an FPGA or ASIC target.

That said, [Ken Shirriff] found a few surprises in the 386’s die, some of which threw him for a loop. An intrinsic part of standard cells is that they’re arranged in rows and columns, with data channels between them where signal paths can be routed. The surprise here was finding a stray PMOS transistor right in the midst of one such data channel, which [Ken] speculates is a bug fix for one of the multiplexers. Back then regenerating the layout would have been rather expensive, so a manual fix like this would have made perfect sense. Consider it a bodge wire for ASICs.

Another oddity was an inverter that wasn’t an inverter, which turned out to be just two separate NMOS and PMOS transistors that looked to be wired up as an inverter, but seemed to actually there as part of a multiplexer. As it turns out, it’s hard to determine sometimes whether transistors are connected in these die teardowns, or whether there’s a gap between them, or just an artifact of the light or the etching process.

Comprehensive Test Set Released For The Intel 80286

July 24, 2025 by 23 Comments

Remember the 80286? It was the sequel to the 8086, the chip that started it all, and it powered a great number of machines in the early years of the personal computing revolution. It might not be as relevant today, but regardless, [Daniel Balsom] has now released a comprehensive test suite for the ancient chip. (via The Register)

The complete battery of tests are available on Github, and were produced using a Harris N80C286-12 from 1986. “The real mode test suite contains 326 instruction forms, containing nearly 1.5 million instruction executions with over 32 million cycle states captured,” Daniel explains. “This is fewer tests than the previous 8088 test suite, but test coverage is better overall due to improved instruction generation methods.” For now, the tests focus on the 286 running in real mode. There are no “unreal” or protected mode tests, but [Daniel] aims to deliver the in the future.

[Daniel] uses the tests with the ArduinoX86, a platform that uses the microcontroller to control and test old-school CPUs. The tests aid with development of emulators like [Daniel’s] own MartyPC, by verifying the CPU’s behavior in a cycle-accurate way.

We’ve explored some secrets of the 286 before, too. If you’ve been doing your own digging into Intel’s old processors, or anyone else’s for that matter, don’t hesitate to notify the tipsline.

[Thanks to Stephen Walters for the tip!]