Medicina Legal, Antropología Física Y Toxicología

In 2008, Salahuddin and Datta [1] proposed that a ferroelectric material operating in the negative capacitance region could act as a step-up converter of the surface potential in a MOS structure, opening a new route for the realization of transistors with steeper subthreshold characteristics (S<60 mV/decade). In this letter, a comprehensive physics-based surface potential and drain current model for the negative capacitance field-effect transistor is reported. The model is aimed to evaluate the potentiality of such transistors for low-power switching applications. Moreover it provides a model core for memories devices relying on the hysteretic behavior of the ferroelectric gate insulator.

In 2008, Salahuddin and Datta [1] proposed that a ferroelectric material operating in the negative capacitance region could act as a step-up converter of the surface potential in a MOS structure, opening a new route for the realization of transistors with steeper subthreshold characteristics (S<60 mV/decade). In this letter, a comprehensive physics-based surface potential and drain current model for the negative capacitance field-effect transistor is reported. The model is aimed to evaluate the potentiality of such transistors for low-power switching applications. Moreover it provides a model core for memories devices relying on the hysteretic behavior of the ferroelectric gate insulator.

Ge metal-oxide semiconductor field effect transistors (MOSFETs) has been developed including the dependencies on the germanium mole fraction, the doping concentration, and the width of the strained-Si layer. We have also obtained a good estimation of the inversion charge. The inclusion of quantum effects in classical simulators by means of a corrected gate-oxide width can be easily performed making use of this new model.

In this work some variants of a deterministic simulation of p-n junctions are considered. From a mathematical point of view, this will be done by means of the numerical resolution of the corresponding Boltzmann transport’s equations (BTE’s): one for the electrons and another one for the holes, coupled by the Poisson equation for the potential, from which the electric field is calculated. In order to improve the efficiency of the Finite-Difference Weighted Essentially Non-Oscillatory (FD-WENO) code, we will consider the two transport equations in the depletion zone and only the corresponding BTE equation for the majority carrier in each one of the neutral zones, instead of solving the two BTE’s in the entire length of the device.

In this work, we develop a comprehensive model of the total gate capacitance (C G ) of circular-cross-section surrounding gate transistors that accounts for both the insulator gate capacitance (C ins ) and the inversion capacitance (C inv ). The accuracy of the model is checked with the results obtained from the numerical simulation of the structure. Using this model, we compare the C G /C ins ratio with that of double-gate (DG) transistors and study the degradation of the total gate capacitance of both devices as a function of the gate voltage and device size. It is shown that the C G /C ins ratio is higher in DGs, particularly for very small devices.

A semiempirical model was developed for calculating the inversion charge of cylindrical surrounding gate transistors (SGTs), including quantum effects. To achieve this goal, we used a simulator that self-consistently solves the 2-D Poisson and Schrödinger equations in a cross section of the SGT. By means of the proposed models, we correctly reproduced the simulation data for a wide range of the device radius and gate voltage values. Both the inversion charge and the centroid models consist of simple mathematical equations within an explicit calculation scheme suitable for use in circuit simulators.

We studied the effect of the depletion charge in the polysilicon gate on electron mobility in ultrathin oxide MOSFETs. An improved theory for remote-charge-scattering-limited mobility in silicon inversion layers is developed. The model takes into account the effects of image charges, screening, inversion layer quantization, the contribution of different subbands, oxide thickness, the actual distribution of charged centres inside the structure, the actual distribution of carriers in the inversion layer, the correlation of charged centres and the charged centre sign. It is shown that if the oxide is thin enough the remote Coulomb scattering due to the depletion charge in the poly-gate becomes an effective scattering mechanism, whose effect is comparable to those of the main scattering mechanisms that control the movement of the carriers in the MOSFET channel. As a consequence, this scattering mechanism must be taken into account in order to satisfactorily explain the experimental results obtained in ultrathin oxide MOSFETs. The model is implemented in a Monte Carlo simulator, where the effects of the ionized impurity charge in the substrate, the interface trapped charge and the contribution of other scattering mechanisms are taken into account simultaneously. Our results show that RCS cannot be neglected for oxide thicknesses below 2 nm, but that its effects for t ox > 5 nm are negligible. Good agreement with experimental results was obtained.

The trend toward continuous integration of the nanometer scale and the rise of nonconventional device concepts such as multigate transistors present important challenges for the semiconductor community. Simulation tools have to be adapted to this new scenario where classical approaches are not sufficiently accurate, and quantum effects have to be taken into account.

In this work, we study the differences caused in the Capacitance-Voltage (C-V) characteristics of MOS devices when SiO2 is replaced by HfO2 as the gate dielectric. A self-consistent Schrödinger-Poisson solver has been developed to include the effects of quantum confinement and the influence of different parameters such as the effective mass, barrier height, and dielectric constant (κ) of the gate insulator material. Two different devices are considered: A Double Gate MOSFET and a Surrounding Gate Transistor. The validity of the Equivalent Oxide Thickness (EOT) is studied.

A new approach to calculate the subthreshold swing of short channel bulk and silicon-on-insulator metal oxide semiconductor ®eld eect transistors is presented. The procedure utilizes a channel-potential expression appropriate for submicron dimensions. The ®nal result is similar to that used for long channels except for a factor k which represents the short channel eects. Comparison with dierent published results reveals excellent quantitative agreement. Ó

In this paper, simulation-based research on the electrostatics of Pi-gate silicon-on-insulator (SOI) MOSFETs is carried out. To do so, a 2-D self-consistent Schrödinger-Poisson solver has been implemented. The inclusion of the quantum effects has been demonstrated to be necessary for the accurate simulation of these devices in the nanometer range. Specifically, this paper is focused on the corner effects in multiple-gate SOI MOSFETs, defined as the formation of independent channels with different threshold voltages. Corner effects are studied as a function of different parameters, such as the doping density, silicon-fin dimensions, corner rounding, and gate oxide thickness. Finally, the relation between corner effects and the transition from a fully to a partially depleted body is analyzed.

A model to study the effect of the roughness at the poly-Si/SiO/sub 2/ interface in silicon inversion layers on the electron mobility is obtained. Screening of the resulting perturbation potential by the channel carriers is taken into account, considering Green's functions for metal-oxide-semiconductor (MOS) geometry, i.e. taking into account the finite thickness of the gate oxide. Mobility of electrons is evaluated at room temperature by the Monte Carlo method, taking into account the simultaneous contribution of phonon scattering, SiO/sub 2//Si interface roughness scattering, Coulomb scattering and remote surface roughness scattering. The contribution of excited subbands is considered. The resulting remote surface roughness scattering is shown to be strongly dependent on the oxide thickness, and degrades mobility curves at low inversion charge concentrations. The results obtained show that the effect of this scattering mechanism cannot be ignored when the oxide thickness is below 5 nm, (as in actual devices), even when (as is usual) very high doping concentrations are used.

A Quantum Ensemble Monte Carlo (QEMC) simulator is used to calculate electrical characteristics and transient response of actual nanotransistors: both sub-50 nm CMOS N-MOSFETs and ultrathin double gate SOI transistors have been deeply studied. Doping profiles and oxide thickness have been selected to cope with the available specifications of the ITRS Roadmap. The Quantum corrected Ensemble Monte Carlo simulator (QEMC) has been used to self-consistently solve the Boltzmann Transport and Poisson equations in actual devices. Quantum effects are included through the Multi-Valley Effective Conduction Band Edge (MV-ECBE) technique, and adequate approaches for phonon and surface roughness scattering have been developed to include the effects of carrier quantization in pseudo-2DEG simulations.

In this work, a self-consistent solution of the 2D Schrödinger-Poisson equations is used to analyze Multiple-Gate MOSFETs. Classical simulations overestimate the peak density compared to quantum simulations and therefore the total electron density considered to calculate the current. The impact of the corner rounding on the electron distribution has also been analyzed. New devices, such as the Omega-gate MOSFETs have been studied as a function of the buried gate length.

The Monte Carlo simulation method is used to analyze the behavior of electron and hole mobility in different nanoelectronic devices including double gate transistors and FinFETs. The impact of technological parameters on carrier mobility is broadly discussed, and its behavior physically explained. Our main goal is to show how mobility in multiple gate devices compares to that in single gate devices and to study different approaches to improve the performance of these devices. Simulations of ultrashort channel devices taking into account quantum effects are also shown.

Electron transport properties in double-gate-silicon-on-insulator (DGSOI) transistors are comprehensively studied. Quantum effects are analyzed by self-consistently solving the 1 D Poisson and Schroedinger equations. Once the electron distribution is known, the Bolztmann transport equation is solved by the Monte Carlo method, and the role of volume inversion is analyzed both at room and at lower temperatures. A comparison between symmetrical-gate and asymmetrical-gate configurations is also provided, showing the superior performance of symmetric devices. Finally, velocity overshoot is also studied. Monte Carlo simulations were performed to clarify the dependence of velocity overshoot effects on the low-field mobility, channel inversion charge and silicon layer thickness. We show that electron mobility is mainly determined by the increase in the phonon scattering rate as the silicon thickness is reduced, i.e., the lower the silicon thickness the lower the electron mobility, while velocity overshoot effects for ultrathin DGSOI inversion layers are dominated by the reduction of the average conduction effective mass, i.e., the lower the silicon thickness the higher the velocity overshoot peak.

Ge metal-oxide semiconductor field effect transistors (MOSFETs) has been developed including the dependencies on the germanium mole fraction, the doping concentration, and the width of the strained-Si layer. We have also obtained a good estimation of the inversion charge. The inclusion of quantum effects in classical simulators by means of a corrected gate-oxide width can be easily performed making use of this new model.

The evolution of traditional metal-oxidesemiconductor field-effect transistors (MOSFETs) from planar single-gate devices into 3-D ones with multiple gates and high-κ insulators imposes the use of new electrical models that accurately reproduce their behavior. This paper demonstrates that the typical expression of equivalent oxide thickness (EOT) for planar devices with high-κ gate insulators becomes useless for nonplanar ones such as triple-gate (trigate) silicon-on-insulator MOSFETs. An alternative expression of the EOT for these trigate devices has been developed through a semianalytical approach to the gateinsulator capacitance. The proposed model correctly reproduces the total electron density in a wide range of device dimensions and applied biases.

Ge metal-oxide semiconductor field effect transistors (MOSFETs) has been developed including the dependencies on the germanium mole fraction, the doping concentration, and the width of the strained-Si layer. We have also obtained a good estimation of the inversion charge. The inclusion of quantum effects in classical simulators by means of a corrected gate-oxide width can be easily performed making use of this new model.

In this work some variants of a deterministic simulation of p-n junctions are considered. From a mathematical point of view, this will be done by means of the numerical resolution of the corresponding Boltzmann transport’s equations (BTE’s): one for the electrons and another one for the holes, coupled by the Poisson equation for the potential, from which the electric field is calculated. In order to improve the efficiency of the Finite-Difference Weighted Essentially Non-Oscillatory (FD-WENO) code, we will consider the two transport equations in the depletion zone and only the corresponding BTE equation for the majority carrier in each one of the neutral zones, instead of solving the two BTE’s in the entire length of the device.