{"title":"Georg's Log - programming","link":[{"@attributes":{"href":"https:\/\/gms.tf\/","rel":"alternate"}},{"@attributes":{"href":"https:\/\/gms.tf\/feeds\/programming.atom.xml","rel":"self"}}],"id":"https:\/\/gms.tf\/","updated":"2020-01-25T00:00:00+01:00","entry":{"title":"Programming with RISC-V Vector Instructions","link":{"@attributes":{"href":"https:\/\/gms.tf\/riscv-vector.html","rel":"alternate"}},"published":"2020-01-25T00:00:00+01:00","updated":"2020-01-25T00:00:00+01:00","author":{"name":"Georg Sauthoff"},"id":"tag:gms.tf,2020-01-25:\/riscv-vector.html","summary":"

Perhaps the most interesting part of the open RISC-V<\/a> instruction set architecture (ISA)<\/a> is the vector extension (RISC-V "V").\nIn contrast to the average single-instruction multipe-data (SIMD)<\/a> instruction set, RISC-V vector instructions are vector length agnostic (VLA).\nThus, a RISC-V "V" CPU is flexible in choosing a vector register size \u2026<\/p>","content":"

Perhaps the most interesting part of the open RISC-V<\/a> instruction set architecture (ISA)<\/a> is the vector extension (RISC-V "V").\nIn contrast to the average single-instruction multipe-data (SIMD)<\/a> instruction set, RISC-V vector instructions are vector length agnostic (VLA).\nThus, a RISC-V "V" CPU is flexible in choosing a vector register size while RISC-V "V" binary code is portable between different CPU implementations.<\/p>\n

This articles compares the two main different styles of vector ISAs, discusses a string processing example that is implemented using RISC-V "V" draft version 0.8<\/a> (current as of early 2020) vector instructions and details how to set up a RISC-V "V" development environment under Linux.<\/p>\n