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rework byval ZIR instructions; forbid runtime vector indexes#25154

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andrewrk merged 40 commits intomasterfrom
no-decl-val-3
Sep 21, 2025
Merged

rework byval ZIR instructions; forbid runtime vector indexes#25154
andrewrk merged 40 commits intomasterfrom
no-decl-val-3

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@andrewrk andrewrk commented Sep 5, 2025

fixes #22906
fixes #13938
fixes #25111
partially addresses #24061 by making vector indexes comptime-known
partially addresses #5973

Upgrade Guide

for (0..vector_len) |i| {
   _ = vector[i];
}

⬇️

// coerce the vector to an array
const vector_type = @typeInfo(@TypeOf(vector)).vector;
const array: [vector_type.len]vector_type.child = vector;
for (&array) |elem| {
    _ = elem;
}

Performance Data Points

llvm backend ReleaseFast compiler building Debug Zig compiler, master vs branch

Benchmark 1 (3 runs): master/bin/zig build-exe ...
  measurement          mean ± σ            min … max           outliers         delta
  wall_time          12.3s  ± 16.2ms    12.3s  … 12.3s           0 ( 0%)        0%
  peak_rss           1.36GB ± 22.5MB    1.34GB … 1.39GB          0 ( 0%)        0%
  cpu_cycles          105G  ±  291M      105G  …  105G           0 ( 0%)        0%
  instructions        212G  ± 3.89M      212G  …  212G           0 ( 0%)        0%
  cache_references   6.67G  ± 19.6M     6.66G  … 6.69G           0 ( 0%)        0%
  cache_misses        466M  ± 5.03M      461M  …  471M           0 ( 0%)        0%
  branch_misses       404M  ± 1.57M      403M  …  406M           0 ( 0%)        0%
Benchmark 2 (3 runs): branch/bin/zig build-exe ...
  measurement          mean ± σ            min … max           outliers         delta
  wall_time          12.9s  ± 36.4ms    12.9s  … 13.0s           0 ( 0%)        💩+  5.1% ±  0.5%
  peak_rss           1.40GB ± 8.90MB    1.40GB … 1.41GB          0 ( 0%)          +  3.0% ±  2.8%
  cpu_cycles          109G  ±  170M      109G  …  109G           0 ( 0%)        💩+  4.2% ±  0.5%
  instructions        221G  ± 5.81M      221G  …  221G           0 ( 0%)        💩+  4.0% ±  0.0%
  cache_references   7.08G  ± 8.88M     7.07G  … 7.09G           0 ( 0%)        💩+  6.1% ±  0.5%
  cache_misses        486M  ± 3.12M      483M  …  489M           0 ( 0%)        💩+  4.4% ±  2.0%
  branch_misses       413M  ± 1.25M      412M  …  414M           0 ( 0%)        💩+  2.1% ±  0.8%

Zig Compiler ReleaseSmall Size

💩 13.6 -> 14.1M (+4%)

The test case from #13938

  • Debug ⚡ 29677949 -> 236675ns (-99%)
  • ReleaseFast ⚡ 28415587 -> 491ns (-100%)

llvm backend ReleaseFast building Debug Zig compiler, using llvm backend vs using x86 backend, with the branch

Benchmark 1 (3 runs): stage3/bin/zig build-exe -fllvm -flld ...
  measurement          mean ± σ            min … max           outliers         delta
  wall_time          60.0s  ± 63.6ms    59.9s  … 60.0s           0 ( 0%)        0%
  peak_rss           4.01GB ±  447KB    4.01GB … 4.01GB          0 ( 0%)        0%
  cpu_cycles          316G  ±  385M      315G  …  316G           0 ( 0%)        0%
  instructions        583G  ±  221M      583G  …  583G           0 ( 0%)        0%
  cache_references   22.4G  ± 49.5M     22.3G  … 22.4G           0 ( 0%)        0%
  cache_misses       4.54G  ± 9.15M     4.53G  … 4.55G           0 ( 0%)        0%
  branch_misses      2.27G  ± 1.79M     2.27G  … 2.27G           0 ( 0%)        0%
Benchmark 2 (3 runs): stage3/bin/zig build-exe -fno-llvm -fno-lld ...
  measurement          mean ± σ            min … max           outliers         delta
  wall_time          13.0s  ± 29.7ms    13.0s  … 13.1s           0 ( 0%)        ⚡- 78.3% ±  0.2%
  peak_rss           1.38GB ± 31.0MB    1.34GB … 1.41GB          0 ( 0%)        ⚡- 65.7% ±  1.2%
  cpu_cycles          111G  ±  136M      110G  …  111G           0 ( 0%)        ⚡- 65.0% ±  0.2%
  instructions        222G  ± 10.5M      222G  …  222G           0 ( 0%)        ⚡- 62.0% ±  0.1%
  cache_references   7.17G  ± 10.5M     7.16G  … 7.18G           0 ( 0%)        ⚡- 67.9% ±  0.4%
  cache_misses        482M  ± 3.52M      478M  …  485M           0 ( 0%)        ⚡- 89.4% ±  0.3%
  branch_misses       424M  ± 1.23M      423M  …  425M           0 ( 0%)        ⚡- 81.3% ±  0.2%

x86 backend Debug compiler building Debug Zig compiler, master vs branch

Benchmark 1 (3 runs): master/stage4/bin/zig build-exe ...
  measurement          mean ± σ            min … max           outliers         delta
  wall_time           423s  ± 4.75s      420s  …  428s           0 ( 0%)        0%
  peak_rss           3.59GB ±  166MB    3.50GB … 3.79GB          0 ( 0%)        0%
  cpu_cycles         3.52T  ±  106G     3.46T  … 3.65T           0 ( 0%)        0%
  instructions       2.67T  ± 84.4G     2.62T  … 2.77T           0 ( 0%)        0%
  cache_references    161G  ± 3.52G      159G  …  165G           0 ( 0%)        0%
  cache_misses       20.0G  ±  336M     19.8G  … 20.4G           0 ( 0%)        0%
  branch_misses      3.88G  ±  116M     3.81G  … 4.01G           0 ( 0%)        0%
Benchmark 2 (3 runs): branch/stage4/bin/zig build-exe ...
  measurement          mean ± σ            min … max           outliers         delta
  wall_time           469s  ± 3.71s      466s  …  473s           0 ( 0%)        💩+ 10.9% ±  2.3%
  peak_rss           3.56GB ± 36.3MB    3.54GB … 3.60GB          0 ( 0%)          -  1.0% ±  7.6%
  cpu_cycles         3.78T  ± 21.7G     3.76T  … 3.80T           0 ( 0%)        💩+  7.2% ±  4.9%
  instructions       2.78T  ± 17.3G     2.77T  … 2.80T           0 ( 0%)          +  4.1% ±  5.2%
  cache_references    170G  ±  602M      169G  …  170G           0 ( 0%)        💩+  5.2% ±  3.6%
  cache_misses       20.4G  ± 50.1M     20.3G  … 20.4G           0 ( 0%)          +  1.6% ±  2.7%
  branch_misses      4.01G  ± 24.3M     3.99G  … 4.04G           0 ( 0%)          +  3.4% ±  4.9%

llvm backend Debug vs x86_64 backend Debug, building a subset of the Debug Zig compiler from this branch

Benchmark 1 (3 runs): master-llvm/bin/zig build-exe ...
  measurement          mean ± σ            min … max           outliers         delta
  wall_time          19.6s  ± 85.8ms    19.5s  … 19.7s           0 ( 0%)        0%
  peak_rss            798MB ± 4.74MB     795MB …  803MB          0 ( 0%)        0%
  cpu_cycles          220G  ±  285M      219G  …  220G           0 ( 0%)        0%
  instructions        485G  ± 5.71M      485G  …  485G           0 ( 0%)        0%
  cache_references   20.2G  ± 12.0M     20.2G  … 20.2G           0 ( 0%)        0%
  cache_misses       1.05G  ± 8.68M     1.04G  … 1.06G           0 ( 0%)        0%
  branch_misses       416M  ±  843K      415M  …  416M           0 ( 0%)        0%
Benchmark 2 (3 runs): master-x86_64/bin/zig build-exe ...
  measurement          mean ± σ            min … max           outliers         delta
  wall_time          58.5s  ±  190ms    58.3s  … 58.7s           0 ( 0%)        💩+198.8% ±  1.7%
  peak_rss            897MB ± 10.6MB     886MB …  907MB          0 ( 0%)        💩+ 12.5% ±  2.3%
  cpu_cycles          645G  ±  921M      644G  …  646G           0 ( 0%)        💩+193.5% ±  0.7%
  instructions        559G  ± 3.89M      559G  …  559G           0 ( 0%)        💩+ 15.2% ±  0.0%
  cache_references   59.8G  ± 28.4M     59.8G  … 59.8G           0 ( 0%)        💩+196.1% ±  0.2%
  cache_misses       3.63G  ± 36.6M     3.60G  … 3.67G           0 ( 0%)        💩+245.3% ±  5.7%
  branch_misses       665M  ± 5.26M      659M  …  669M           0 ( 0%)        💩+ 60.1% ±  2.1%
Benchmark 1 (3 runs): branch-llvm/llvm/bin/zig build-exe ...
  measurement          mean ± σ            min … max           outliers         delta
  wall_time          28.2s  ± 1.17s     27.5s  … 29.6s           0 ( 0%)        0%
  peak_rss            960MB ±  199MB     841MB … 1.19GB          0 ( 0%)        0%
  cpu_cycles          314G  ± 36.3G      293G  …  356G           0 ( 0%)        0%
  instructions        611G  ± 74.2G      568G  …  696G           0 ( 0%)        0%
  cache_references   26.9G  ± 2.43G     25.5G  … 29.8G           0 ( 0%)        0%
  cache_misses       1.60G  ±  127M     1.52G  … 1.75G           0 ( 0%)        0%
  branch_misses       518M  ±  103M      458M  …  637M           0 ( 0%)        0%
Benchmark 2 (3 runs): branch-x86_64/debug/bin/zig build-exe ...
  measurement          mean ± σ            min … max           outliers         delta
  wall_time          70.9s  ± 2.95s     69.0s  … 74.3s           0 ( 0%)        💩+151.1% ± 18.0%
  peak_rss            992MB ±  210MB     866MB … 1.23GB          0 ( 0%)          +  3.3% ± 48.3%
  cpu_cycles          775G  ± 91.2G      721G  …  880G           0 ( 0%)        💩+146.6% ± 50.1%
  instructions        655G  ± 94.2G      601G  …  764G           0 ( 0%)          +  7.3% ± 31.5%
  cache_references   69.1G  ± 5.49G     65.6G  … 75.4G           0 ( 0%)        💩+156.4% ± 35.7%
  cache_misses       3.85G  ±  195M     3.74G  … 4.08G           0 ( 0%)        💩+141.0% ± 23.4%
  branch_misses       991M  ±  144M      903M  … 1.16G           0 ( 0%)        💩+ 91.4% ± 55.0%

@andrewrk andrewrk added breaking Implementing this issue could cause existing code to no longer compile or have different behavior. release notes This PR should be mentioned in the release notes. labels Sep 5, 2025
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andrewrk commented Sep 5, 2025

How about on this branch @jacobly0 can you repro the x86 backend failures the CI is running into?

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jacobly0 commented Sep 5, 2025

--- a/src/arch/x86_64/CodeGen.zig
+++ b/src/arch/x86_64/CodeGen.zig
@@ -92414,7 +92414,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void {
                     .clobbers = .{ .eflags = true },
                     .each = .{ .once = &.{
                         .{ ._, ._, .mov, .tmp0p, .sa(.src0, .sub_unaligned_size), ._, ._ },
-                        .{ .@"0:", .vp_d, .movzxb, .tmp1y, .memia(.src0x, .tmp0, .add_unaligned_size), ._, ._ },
+                        .{ .@"0:", .vp_d, .movzxb, .tmp1y, .memia(.src0q, .tmp0, .add_unaligned_size), ._, ._ },
                         .{ ._, .v_dqa, .mov, .memsia(.dst0y, .@"4", .tmp0, .add_unaligned_size), .tmp1y, ._, ._ },
                         .{ ._, ._, .add, .tmp0p, .si(8), ._, ._ },
                         .{ ._, ._nc, .j, .@"0b", ._, ._, ._ },

@andrewrk andrewrk force-pushed the no-decl-val-3 branch 2 times, most recently from b7e95f3 to d8dfa7b Compare September 6, 2025 02:59
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andrewrk commented Sep 6, 2025

lots of this triggered by test-cases:

/home/andy/dev/zig/lib/std/Io/Writer.zig:342:5: error: unimplemented ptr_slice_len_ptr
pub fn defaultRebase(w: *Writer, preserve: usize, minimum_len: usize) Error!void {
~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

from src/codegen/aarch64/Select.zig line 964

@andrewrk andrewrk force-pushed the no-decl-val-3 branch 2 times, most recently from e0bdebd to 6741734 Compare September 6, 2025 06:07
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See comments.


This change also regresses unused variable errors in some cases, such as:

var x: [1]u8 = .{0};
_ = x[0];

and:

const x: S = .{ .y = 0 };
_ = x.y;

I definitely mentioned this to you months ago, but I can forgive you forgetting that 😛
This requires some bigger AstGen changes to fix; I recommend opening a follow-up issue after merge and I'll get to it when I can.

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andrewrk commented Sep 6, 2025

Blocking on #25172, which also affects master branch.

@andrewrk andrewrk force-pushed the no-decl-val-3 branch 3 times, most recently from 33cc67d to f3a3dc6 Compare September 8, 2025 03:24
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andrewrk commented Sep 8, 2025

Some aarch64 backend failures in the x86_64-linux-debug-llvm run

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jacobly0 commented Sep 8, 2025

Some aarch64 backend failures in the x86_64-linux-debug-llvm run

Those are all ptr_add/ptr_sub of pointers to zero-bit types which nobody has convinced me should be valid Air (although ironically the aarch64 backend design is the best equipped to handle that without harming codegen quality, but that isn't really a good enough reason to assume it should be allowed).

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andrewrk commented Sep 8, 2025

Understood; will remedy that as a prereq to making progress here then.

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jacobly0 commented Sep 8, 2025

I guess an argument in favor of not allowing them is that the index operand is dead in a way that is not reflected in Air.Liveness, which affects the output size of the llvm and c backends which are not likely to be rewritten to not use Air.Liveness anytime soon.

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andrewrk commented Sep 9, 2025

Have a reduction handy? It's not one of the examples from #22419 and from looking at Sema.zig I can see only these code paths emit those instructions:

  • arithmetic, but that's protected by error: pointer arithmetic requires element type 'void' to have runtime bits
  • array concatenation
  • memcpy safety
  • slice syntax

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jacobly0 commented Sep 9, 2025

idk just

--- a/src/Sema.zig
+++ b/src/Sema.zig
@@ -809,6 +809,10 @@ pub const Block = struct {
     }
 
     pub fn addInst(block: *Block, inst: Air.Inst) error{OutOfMemory}!Air.Inst.Ref {
+        switch (inst.tag) {
+            else => {},
+            .ptr_add, .ptr_sub => assert(block.sema.typeOf(@enumFromInt(block.sema.air_extra.items[inst.data.ty_pl.payload])).childType(block.sema.pt.zcu).hasRuntimeBitsSema(block.sema.pt) catch unreachable),
+        }
         return (try block.addInstAsIndex(inst)).toRef();
     }
 

and run the behavior tests, looks like it is just calls to analyzePtrArithmetic that are not from analyzeArithmetic which is what checks for that error.

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andrewrk commented Sep 9, 2025

Good idea. Yeah it was a pretty trivial fix actually. Seems to be just one missing check inside analyzePtrArithmetic.

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andrewrk commented Sep 9, 2025

Disabling spirv64-vulkan coverage due to no active maintainer:

test
+- test-modules
   +- test-behavior
      +- compile test Debug spirv64-vulkan 29 errors
/home/ci/actions-runner4/_work/zig/zig/lib/std/testing.zig:362:38: error: cannot access element of logical pointer '[]const u64'
            if (!std.meta.eql(actual[index], expected[index])) break :diff_index index;
                                     ^~~~~
referenced by:
    expectEqualInner__anon_4105: /home/ci/actions-runner4/_work/zig/zig/lib/std/testing.zig:140:34
    expectEqual [inlined]: /home/ci/actions-runner4/_work/zig/zig/lib/std/testing.zig:75:28
    test.peer type resolution: array with smaller child type and vector with larger child type: /home/ci/actions-runner4/_work/zig/zig/test/behavior/cast.zig:1779:20
/home/ci/actions-runner4/_work/zig/zig/lib/std/testing.zig:362:38: error: cannot access element of logical pointer '[]const i32'
            if (!std.meta.eql(actual[index], expected[index])) break :diff_index index;
                                     ^~~~~
/home/ci/actions-runner4/_work/zig/zig/lib/std/testing.zig:362:38: error: cannot access element of logical pointer '[]const f32'
            if (!std.meta.eql(actual[index], expected[index])) break :diff_index index;
                                     ^~~~~
/home/ci/actions-runner4/_work/zig/zig/lib/std/testing.zig:362:38: error: cannot access element of logical pointer '[]const u32'
            if (!std.meta.eql(actual[index], expected[index])) break :diff_index index;
                                     ^~~~~
/home/ci/actions-runner4/_work/zig/zig/lib/std/testing.zig:362:38: error: cannot access element of logical pointer '[]const u1'
            if (!std.meta.eql(actual[index], expected[index])) break :diff_index index;
                                     ^~~~~
/home/ci/actions-runner4/_work/zig/zig/lib/std/testing.zig:362:38: error: cannot access element of logical pointer '[]const u8'
            if (!std.meta.eql(actual[index], expected[index])) break :diff_index index;
                                     ^~~~~
/home/ci/actions-runner4/_work/zig/zig/lib/std/testing.zig:362:38: error: cannot access element of logical pointer '[]const bool'
            if (!std.meta.eql(actual[index], expected[index])) break :diff_index index;
                                     ^~~~~
/home/ci/actions-runner4/_work/zig/zig/test/behavior/cast.zig:462:19: error: value with non-mergable pointer type '*const ?behavior.cast.A' depends on runtime control flow
    try expect((b catch unreachable).?.a == 1);
                ~~^~~~~~~~~~~~~~~~~
/home/ci/actions-runner4/_work/zig/zig/test/behavior/cast.zig:462:19: note: runtime control flow here
/home/ci/actions-runner4/_work/zig/zig/test/behavior/cast.zig:462:19: note: pointers with address space 'generic' cannot be returned from a branch on target spirv-vulkan by compiler backend stage2_spirv
/home/ci/actions-runner4/_work/zig/zig/test/behavior/cast.zig:473:35: error: value with non-mergable pointer type '*const []u8' depends on runtime control flow
    try expect((gimmeErrOrSlice() catch unreachable).len == 0);
                ~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~
/home/ci/actions-runner4/_work/zig/zig/test/behavior/cast.zig:473:35: note: runtime control flow here
/home/ci/actions-runner4/_work/zig/zig/test/behavior/cast.zig:473:35: note: pointers with address space 'generic' cannot be returned from a branch on target spirv-vulkan by compiler backend stage2_spirv
/home/ci/actions-runner4/_work/zig/zig/test/behavior/cast.zig:1270:19: error: value with non-mergable pointer type '*[]const u8' depends on runtime control flow
    try expect((x catch unreachable).len == 0);
                ~~^~~~~~~~~~~~~~~~~
/home/ci/actions-runner4/_work/zig/zig/test/behavior/cast.zig:1270:19: note: runtime control flow here
/home/ci/actions-runner4/_work/zig/zig/test/behavior/cast.zig:1270:19: note: pointers with address space 'generic' cannot be returned from a branch on target spirv-vulkan by compiler backend stage2_spirv
/home/ci/actions-runner4/_work/zig/zig/test/behavior/array.zig:44:1: error: TODO (SPIR-V): implement AIR tag ptr_slice_len_ptr
fn getArrayLen(a: []const u32) usize {
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/ci/actions-runner4/_work/zig/zig/test/behavior/array.zig:260:1: error: TODO (SPIR-V): implement AIR tag ptr_slice_len_ptr
test "implicit cast zero sized array ptr to slice" {
^~~~
/home/ci/actions-runner4/_work/zig/zig/test/behavior/bitcast.zig:177:9: error: TODO (SPIR-V): implement field access for packed structs
        fn doTheTest() !void {
        ^~~~~~~~~~~~~~~~~~~~
/home/ci/actions-runner4/_work/zig/zig/test/behavior/bitcast.zig:233:9: error: TODO (SPIR-V): implement field access for packed structs
        fn doTheTest() !void {
        ^~~~~~~~~~~~~~~~~~~~
/home/ci/actions-runner4/_work/zig/zig/test/behavior/cast.zig:1444:1: error: TODO (SPIR-V): implement AIR tag ptr_slice_len_ptr
test "coerce undefined single-item pointer of array to error union of slice" {
^~~~
/home/ci/actions-runner4/_work/zig/zig/test/behavior/cast.zig:1454:1: error: TODO (SPIR-V): implement AIR tag ptr_slice_len_ptr
test "pointer to empty struct literal to mutable slice" {
^~~~
/home/ci/actions-runner4/_work/zig/zig/test/behavior/fn.zig:406:1: error: TODO (SPIR-V): implement AIR tag ptr_slice_len_ptr
test "import passed byref to function in return type" {
^~~~
/home/ci/actions-runner4/_work/zig/zig/test/behavior/fn.zig:450:9: error: TODO (SPIR-V): implement AIR tag try_ptr
        fn errUnion(s: anyerror!@This()) !void {
        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/ci/actions-runner4/_work/zig/zig/test/behavior/packed-struct.zig:251:1: error: cannot perform pointer cast: '*behavior.packed-struct.test.nested packed struct unaligned.S2' to '*align(1:0:2) u4'
test "nested packed struct unaligned" {
^~~~
/home/ci/actions-runner4/_work/zig/zig/test/behavior/packed-struct.zig:898:9: error: TODO (SPIR-V): implement field access for packed structs
        fn foo(p: Packed, a1: u64, a2: u64, a3: u64, a4: u64, a5: u64) callconv(.c) bool {
        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/ci/actions-runner4/_work/zig/zig/test/behavior/packed-struct.zig:970:1: error: TODO (SPIR-V): implement field access for packed structs
test "store undefined to packed result location" {
^~~~
/home/ci/actions-runner4/_work/zig/zig/test/behavior/slice.zig:75:1: error: TODO (SPIR-V): implement AIR tag ptr_slice_len_ptr
fn assertLenIsZero(msg: []const u8) !void {
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/ci/actions-runner4/_work/zig/zig/test/behavior/slice.zig:265:1: error: TODO (SPIR-V): implement AIR tag ptr_slice_len_ptr
test "result location zero sized array inside struct field implicit cast to slice" {
^~~~
/home/ci/actions-runner4/_work/zig/zig/test/behavior/struct.zig:1009:9: error: TODO (SPIR-V): implement field access for packed structs
        fn doTheTest() !void {
        ^~~~~~~~~~~~~~~~~~~~
/home/ci/actions-runner4/_work/zig/zig/lib/std/testing.zig:78:1: error: TODO (SPIR-V): implement field access for packed structs
fn expectEqualInner(comptime T: type, expected: T, actual: T) !void {
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/ci/actions-runner4/_work/zig/zig/test/behavior/union.zig:1348:9: error: TODO (SPIR-V): implement field access for packed structs
        fn unpack(self: @This()) usize {
        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/ci/actions-runner4/_work/zig/zig/test/behavior/union.zig:1904:1: error: TODO (SPIR-V): implement field access for packed structs
test "packed union initialized via reintepreted struct field initializer" {
^~~~
/home/ci/actions-runner4/_work/zig/zig/test/behavior/union.zig:1947:1: error: TODO (SPIR-V): implement field access for packed structs
test "store of comptime reinterpreted memory to packed union" {
^~~~
/home/ci/actions-runner4/_work/zig/zig/test/behavior/vector.zig:1266:1: error: TODO (SPIR-V): implement AIR tag mul_sat
test "zero multiplicand" {
^~~~
error: the following command failed with 29 compilation errors:
/home/ci/actions-runner4/_work/zig/zig/build-debug/stage3-debug/bin/zig test -fno-llvm -fno-lld -ODebug -target spirv64-vulkan -mcpu vulkan_v1_2+float16+float64 -Mroot=/home/ci/actions-runner4/_work/zig/zig/test/behavior.zig --cache-dir /home/ci/actions-runner4/_work/zig/zig/zig-local-cache --global-cache-dir /home/ci/actions-runner4/_work/zig/zig/zig-global-cache --name test -L /home/ci/deps/zig+llvm+lld+clang-x86_64-linux-musl-0.16.0-dev.104+689461e31/lib -I /home/ci/deps/zig+llvm+lld+clang-x86_64-linux-musl-0.16.0-dev.104+689461e31/include --zig-lib-dir /home/ci/actions-runner4/_work/zig/zig/lib --listen=-

As soon as someone steps up and fixes it, coverage can be reinstated.

@andrewrk
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andrewrk commented Sep 9, 2025

Disabling wasm backend coverage due to no active maintainer:

test
+- test-modules
   +- test-behavior
      +- run test behavior-wasm32-wasi-none-lime1-Debug-selfhosted-no-lld failure
Error: failed to run main module `/home/ci/actions-runner7/_work/zig/zig/zig-local-cache/o/2b0ea36eeaad87895fcb86b02fb65fc2/test.wasm`

Caused by:
    0: failed to instantiate "/home/ci/actions-runner7/_work/zig/zig/zig-local-cache/o/2b0ea36eeaad87895fcb86b02fb65fc2/test.wasm"
    1: error while executing at wasm backtrace:
           0: 0x14a659 - <unknown>!behavior.union.test.signed enum tag with negative value
           1: 0x5fd2 - <unknown>!test_runner.mainServer
           2: 0x6599 - <unknown>!test_runner.main
           3: 0x29cd - <unknown>!start.wasi_start
    2: wasm trap: wasm `unreachable` instruction executed
error: while executing test 'behavior.union.test.signed enum tag with negative value', the following command exited with code 134 (expected exited with code 0):
wasmtime --dir=. -- /home/ci/actions-runner7/_work/zig/zig/zig-local-cache/o/2b0ea36eeaad87895fcb86b02fb65fc2/test.wasm --cache-dir=/home/ci/actions-runner7/_work/zig/zig/zig-local-cache --seed=0x904666fb --listen=-

As soon as someone steps up and fixes it, coverage can be reinstated. Meanwhile, I'm personally prioritizing stabilizing the language over completing the wasm backend.

@jacobly0
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jacobly0 commented Sep 9, 2025

current partial progress:

--- a/src/arch/x86_64/CodeGen.zig
+++ b/src/arch/x86_64/CodeGen.zig
@@ -186938,7 +186938,7 @@ const Temp = struct {
                 },
                 .struct_type => {
                     assert(src_regs.len - part_index == std.math.divCeil(u32, src_abi_size, 8) catch unreachable);
-                    break :part_ty .u64;
+                    break :part_ty if (src_abi_size <= 4) .u32 else .u64;
                 },
                 .tuple_type => |tuple_type| {
                     assert(tuple_type.types.len == src_regs.len);
@@ -186947,10 +186947,6 @@ const Temp = struct {
             };
             const part_size: u31 = @intCast(part_ty.abiSize(zcu));
             const src_rc = src_reg.class();
-            const part_bit_size = switch (src_rc) {
-                else => 8 * part_size,
-                .x87 => part_ty.bitSize(zcu),
-            };
             if (src_rc == .x87 or std.math.isPowerOfTwo(part_size)) {
                 // hack around linker relocation bugs
                 switch (ptr.tracking(cg).short) {
@@ -186959,7 +186955,10 @@ const Temp = struct {
                 }
                 const strat = try cg.moveStrategy(part_ty, src_rc, false);
                 try strat.write(cg, try ptr.tracking(cg).short.deref().mem(cg, .{
-                    .size = .fromBitSize(part_bit_size),
+                    .size = switch (src_rc) {
+                        else => .fromBitSize(8 * part_size),
+                        .x87 => .tbyte,
+                    },
                     .disp = part_disp,
                 }), registerAlias(src_reg, part_size));
             } else {

Edit: Oh, it works fine, I was just testing wrong.

@andrewrk andrewrk enabled auto-merge September 21, 2025 02:02
@andrewrk andrewrk merged commit 010d9a6 into master Sep 21, 2025
12 of 14 checks passed
@andrewrk andrewrk deleted the no-decl-val-3 branch September 21, 2025 08:49
noxabellus added a commit to noxabellus/zgpu that referenced this pull request Oct 29, 2025
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