rework byval ZIR instructions; forbid runtime vector indexes#25154
rework byval ZIR instructions; forbid runtime vector indexes#25154
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How about on this branch @jacobly0 can you repro the x86 backend failures the CI is running into? |
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--- a/src/arch/x86_64/CodeGen.zig
+++ b/src/arch/x86_64/CodeGen.zig
@@ -92414,7 +92414,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void {
.clobbers = .{ .eflags = true },
.each = .{ .once = &.{
.{ ._, ._, .mov, .tmp0p, .sa(.src0, .sub_unaligned_size), ._, ._ },
- .{ .@"0:", .vp_d, .movzxb, .tmp1y, .memia(.src0x, .tmp0, .add_unaligned_size), ._, ._ },
+ .{ .@"0:", .vp_d, .movzxb, .tmp1y, .memia(.src0q, .tmp0, .add_unaligned_size), ._, ._ },
.{ ._, .v_dqa, .mov, .memsia(.dst0y, .@"4", .tmp0, .add_unaligned_size), .tmp1y, ._, ._ },
.{ ._, ._, .add, .tmp0p, .si(8), ._, ._ },
.{ ._, ._nc, .j, .@"0b", ._, ._, ._ }, |
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lots of this triggered by test-cases: from src/codegen/aarch64/Select.zig line 964 |
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There was a problem hiding this comment.
See comments.
This change also regresses unused variable errors in some cases, such as:
var x: [1]u8 = .{0};
_ = x[0];and:
const x: S = .{ .y = 0 };
_ = x.y;I definitely mentioned this to you months ago, but I can forgive you forgetting that 😛
This requires some bigger AstGen changes to fix; I recommend opening a follow-up issue after merge and I'll get to it when I can.
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Blocking on #25172, which also affects master branch. |
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Some aarch64 backend failures in the x86_64-linux-debug-llvm run |
Those are all |
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Understood; will remedy that as a prereq to making progress here then. |
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I guess an argument in favor of not allowing them is that the index operand is dead in a way that is not reflected in |
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Have a reduction handy? It's not one of the examples from #22419 and from looking at Sema.zig I can see only these code paths emit those instructions:
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idk just --- a/src/Sema.zig
+++ b/src/Sema.zig
@@ -809,6 +809,10 @@ pub const Block = struct {
}
pub fn addInst(block: *Block, inst: Air.Inst) error{OutOfMemory}!Air.Inst.Ref {
+ switch (inst.tag) {
+ else => {},
+ .ptr_add, .ptr_sub => assert(block.sema.typeOf(@enumFromInt(block.sema.air_extra.items[inst.data.ty_pl.payload])).childType(block.sema.pt.zcu).hasRuntimeBitsSema(block.sema.pt) catch unreachable),
+ }
return (try block.addInstAsIndex(inst)).toRef();
}
and run the behavior tests, looks like it is just calls to |
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Good idea. Yeah it was a pretty trivial fix actually. Seems to be just one missing check inside |
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Disabling spirv64-vulkan coverage due to no active maintainer: As soon as someone steps up and fixes it, coverage can be reinstated. |
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Disabling wasm backend coverage due to no active maintainer: As soon as someone steps up and fixes it, coverage can be reinstated. Meanwhile, I'm personally prioritizing stabilizing the language over completing the wasm backend. |
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current partial progress: --- a/src/arch/x86_64/CodeGen.zig
+++ b/src/arch/x86_64/CodeGen.zig
@@ -186938,7 +186938,7 @@ const Temp = struct {
},
.struct_type => {
assert(src_regs.len - part_index == std.math.divCeil(u32, src_abi_size, 8) catch unreachable);
- break :part_ty .u64;
+ break :part_ty if (src_abi_size <= 4) .u32 else .u64;
},
.tuple_type => |tuple_type| {
assert(tuple_type.types.len == src_regs.len);
@@ -186947,10 +186947,6 @@ const Temp = struct {
};
const part_size: u31 = @intCast(part_ty.abiSize(zcu));
const src_rc = src_reg.class();
- const part_bit_size = switch (src_rc) {
- else => 8 * part_size,
- .x87 => part_ty.bitSize(zcu),
- };
if (src_rc == .x87 or std.math.isPowerOfTwo(part_size)) {
// hack around linker relocation bugs
switch (ptr.tracking(cg).short) {
@@ -186959,7 +186955,10 @@ const Temp = struct {
}
const strat = try cg.moveStrategy(part_ty, src_rc, false);
try strat.write(cg, try ptr.tracking(cg).short.deref().mem(cg, .{
- .size = .fromBitSize(part_bit_size),
+ .size = switch (src_rc) {
+ else => .fromBitSize(8 * part_size),
+ .x87 => .tbyte,
+ },
.disp = part_disp,
}), registerAlias(src_reg, part_size));
} else {Edit: Oh, it works fine, I was just testing wrong. |
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It wasn't checking bit pointer data.
If the `nav_ty` is resolved by the `nav_val`, then we need to also mark the `nav_ty` as in progress when we begin resolving the `nav_val`.
This reverts commit ba4d460.
The latest bugfix reverted this case to its old behavior (which is a reasonable behavior to have).
it was calculating host integer size in a wrong way. just use integer abi size
This reverts commit dedccec.
tracked by #24061 - these should be re-enabled once that is solved.
...of array passed as arg closes #22906
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…in GpuGrid.Manager * See this issue for details ziglang/zig#25154
fixes #22906
fixes #13938
fixes #25111
partially addresses #24061 by making vector indexes comptime-known
partially addresses #5973
Upgrade Guide
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Performance Data Points
llvm backend ReleaseFast compiler building Debug Zig compiler, master vs branch
Zig Compiler ReleaseSmall Size
💩 13.6 -> 14.1M (+4%)
The test case from #13938
llvm backend ReleaseFast building Debug Zig compiler, using llvm backend vs using x86 backend, with the branch
x86 backend Debug compiler building Debug Zig compiler, master vs branch
llvm backend Debug vs x86_64 backend Debug, building a subset of the Debug Zig compiler from this branch