[lora] Auto-tune config for MoE LoRA shrink split-K kernel#2
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Adds an offline tuner and a runtime config loader for
_moe_lora_shrink_splitk_kernel (the LoRA-A shrink stage of the merged-experts
MoE LoRA path), mirroring the fused_moe_triton config layout.
- benchmark/kernels/lora_moe_shrink/: tuner that sweeps num_warps / num_stages /
SPLIT_K (and BLOCK_SIZE_M for prefill), pins BLOCK_SIZE_N=rank and
BLOCK_SIZE_K=256, prunes configs over the device SMEM cap, and times with
CUDA-graph amortization (the kernel is us-scale, so per-launch overhead must be
removed). Benchmark routing is seeded for reproducibility.
- moe_lora_shrink_config.py: loads configs keyed by (E, N, K, device); within a
file the entry for the closest token count M is used.
- virtual_experts.py: the shrink stage now prefers the tuned config (including
SPLIT_K), and the same BLOCK_SIZE_M is used to align the MoE routing so the
routing and kernel block sizes stay consistent. Heuristic fallback unchanged.
- moe_shrink_configs/triton_3_6_0/: tuned configs for E in {96,192,384} x
rank {16,32,64} x hidden 7168 on NVIDIA B200.
Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>
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Re-tuned E=96 (rank 16/32/64, K=7168) with a dense small-batch decode grid
(M = 1..8, 16, 24, 32, 48, 64) instead of just {16,32,64}. At small batch the
active-block count scales with M (grid is under-saturated, bs*top_k < E), so the
optimal split_k differs from the saturated regime: e.g. E=96/N=16 M=1 is 3.86us
@ split_k=7 vs 6.60us for the M=16 config it previously snapped to. Tuned
serially with seeded routing on NVIDIA B200.
Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>
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Superseded by upstream PR sgl-project#26899. |
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Auto-tune config for the MoE LoRA shrink split-K kernel
Adds offline tuning + a runtime config loader for
_moe_lora_shrink_splitk_kernel(the LoRA-A / shrink stage of the merged-experts MoE LoRA path), mirroring the
fused_moe_tritonconfig layout.What's included
benchmark/kernels/lora_moe_shrink/— tuner that sweepsnum_warps,num_stages, andSPLIT_K(plusBLOCK_SIZE_Min the prefill regime), withBLOCK_SIZE_Npinned to the rank andBLOCK_SIZE_K=256. It prunes configs thatexceed the device shared-memory cap and times with CUDA-graph amortization
(the kernel is sub-10 µs, so per-launch overhead must be amortized away).
Benchmark routing is seeded for reproducibility.
moe_lora_shrink_config.py— loads configs keyed by(E, N, K, device);within a file it selects the entry for the closest token count
M.virtual_experts.py— the shrink stage now prefers the tuned config(including
SPLIT_K), and the sameBLOCK_SIZE_Mis reused to align the MoErouting so the routing and kernel block sizes stay consistent. The heuristic
fallback (when no tuned file exists) is unchanged.
moe_shrink_configs/triton_3_6_0/— tuned configs forE ∈ {96, 192, 384} × rank ∈ {16, 32, 64} × hidden = 7168on NVIDIA B200.Kernel latencies (NVIDIA B200, bf16, triton 3.6.0, CUDA-graph amortized)
Mis the config key = number of input tokens; in decodeMequals the batchsize (1 token/request), in prefill it is the total token count.
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Latest PR Test (Base): ❌ Run #26739997874
Latest PR Test (Extra): ❌ Run #26739997813