Skip to content

Commit f4ff257

Browse files
moore-brosmbgg
moore-bros
authored and
mbgg
committed
arm: dts: mt7623: add support for Bananapi R2 (BPI-R2) board
Add support for the Bananapi R2 (BPI-R2) development board from BIPAI KEJI. Detailed hardware information for BPI-R2 which could be found on http://www.banana-pi.org/r2.html The patch added nodes into the SoC-level file mt7623.dtsi such as CPU OPP table and thermal zone treating CPU as one of cooling devices and also added nodes into board-level file mt7623n-bananapi-bpi-r2.dts such as MediaTek GMAC, MT7530 Switch, the crypto engine, USB, IR, I2S, I2C, UART, SPI, PWM, GPIO keys, GPIO LEDs and PMIC LEDs. As to the other missing hardware and peripherals, they would be added and integrated continuously. Signed-off-by: Sean Wang <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Matthias Brugger <[email protected]>
1 parent 876680c commit f4ff257

4 files changed

Lines changed: 561 additions & 5 deletions

File tree

‎Documentation/devicetree/bindings/arm/mediatek.txt‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,8 @@ Supported boards:
4949
- Reference board for MT7623n with NAND:
5050
Required root node properties:
5151
- compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
52+
- Bananapi BPI-R2 board:
53+
- compatible = "bananapi,bpi-r2", "mediatek,mt7623";
5254
- MTK mt8127 tablet moose EVB:
5355
Required root node properties:
5456
- compatible = "mediatek,mt8127-moose", "mediatek,mt8127";

‎arch/arm/boot/dts/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1050,6 +1050,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
10501050
mt6589-aquaris5.dtb \
10511051
mt6592-evb.dtb \
10521052
mt7623n-rfb-nand.dtb \
1053+
mt7623n-bananapi-bpi-r2.dtb \
10531054
mt8127-moose.dtb \
10541055
mt8135-evbp1.dtb
10551056
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb

‎arch/arm/boot/dts/mt7623.dtsi‎

Lines changed: 115 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -21,12 +21,58 @@
2121
#include <dt-bindings/gpio/gpio.h>
2222
#include <dt-bindings/phy/phy.h>
2323
#include <dt-bindings/reset/mt2701-resets.h>
24+
#include <dt-bindings/thermal/thermal.h>
2425
#include "skeleton64.dtsi"
2526

2627
/ {
2728
compatible = "mediatek,mt7623";
2829
interrupt-parent = <&sysirq>;
2930

31+
cpu_opp_table: opp_table {
32+
compatible = "operating-points-v2";
33+
opp-shared;
34+
35+
opp-98000000 {
36+
opp-hz = /bits/ 64 <98000000>;
37+
opp-microvolt = <1050000>;
38+
};
39+
40+
opp-198000000 {
41+
opp-hz = /bits/ 64 <198000000>;
42+
opp-microvolt = <1050000>;
43+
};
44+
45+
opp-398000000 {
46+
opp-hz = /bits/ 64 <398000000>;
47+
opp-microvolt = <1050000>;
48+
};
49+
50+
opp-598000000 {
51+
opp-hz = /bits/ 64 <598000000>;
52+
opp-microvolt = <1050000>;
53+
};
54+
55+
opp-747500000 {
56+
opp-hz = /bits/ 64 <747500000>;
57+
opp-microvolt = <1050000>;
58+
};
59+
60+
opp-1040000000 {
61+
opp-hz = /bits/ 64 <1040000000>;
62+
opp-microvolt = <1150000>;
63+
};
64+
65+
opp-1196000000 {
66+
opp-hz = /bits/ 64 <1196000000>;
67+
opp-microvolt = <1200000>;
68+
};
69+
70+
opp-1300000000 {
71+
opp-hz = /bits/ 64 <1300000000>;
72+
opp-microvolt = <1300000>;
73+
};
74+
};
75+
3076
cpus {
3177
#address-cells = <1>;
3278
#size-cells = <0>;
@@ -36,21 +82,31 @@
3682
device_type = "cpu";
3783
compatible = "arm,cortex-a7";
3884
reg = <0x0>;
85+
clocks = <&infracfg CLK_INFRA_CPUSEL>,
86+
<&apmixedsys CLK_APMIXED_MAINPLL>;
87+
clock-names = "cpu", "intermediate";
88+
operating-points-v2 = <&cpu_opp_table>;
89+
#cooling-cells = <2>;
90+
cooling-min-level = <0>;
91+
cooling-max-level = <7>;
3992
};
4093
cpu1: cpu@1 {
4194
device_type = "cpu";
4295
compatible = "arm,cortex-a7";
4396
reg = <0x1>;
97+
operating-points-v2 = <&cpu_opp_table>;
4498
};
4599
cpu2: cpu@2 {
46100
device_type = "cpu";
47101
compatible = "arm,cortex-a7";
48102
reg = <0x2>;
103+
operating-points-v2 = <&cpu_opp_table>;
49104
};
50105
cpu3: cpu@3 {
51106
device_type = "cpu";
52107
compatible = "arm,cortex-a7";
53108
reg = <0x3>;
109+
operating-points-v2 = <&cpu_opp_table>;
54110
};
55111
};
56112

@@ -74,6 +130,56 @@
74130
clock-output-names = "clk26m";
75131
};
76132

133+
thermal-zones {
134+
cpu_thermal: cpu_thermal {
135+
polling-delay-passive = <1000>;
136+
polling-delay = <1000>;
137+
138+
thermal-sensors = <&thermal 0>;
139+
140+
trips {
141+
cpu_passive: cpu_passive {
142+
temperature = <47000>;
143+
hysteresis = <2000>;
144+
type = "passive";
145+
};
146+
147+
cpu_active: cpu_active {
148+
temperature = <67000>;
149+
hysteresis = <2000>;
150+
type = "active";
151+
};
152+
153+
cpu_hot: cpu_hot {
154+
temperature = <87000>;
155+
hysteresis = <2000>;
156+
type = "hot";
157+
};
158+
159+
cpu_crit {
160+
temperature = <107000>;
161+
hysteresis = <2000>;
162+
type = "critical";
163+
};
164+
};
165+
166+
cooling-maps {
167+
map0 {
168+
trip = <&cpu_passive>;
169+
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
170+
};
171+
map1 {
172+
trip = <&cpu_active>;
173+
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
174+
};
175+
map2 {
176+
trip = <&cpu_hot>;
177+
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
178+
};
179+
};
180+
};
181+
};
182+
77183
timer {
78184
compatible = "arm,armv7-timer";
79185
interrupt-parent = <&gic>;
@@ -172,7 +278,7 @@
172278
clock-names = "spi", "wrap";
173279
};
174280

175-
cir: cir@0x10013000 {
281+
cir: cir@10013000 {
176282
compatible = "mediatek,mt7623-cir";
177283
reg = <0 0x10013000 0 0x1000>;
178284
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
@@ -193,7 +299,7 @@
193299
efuse: efuse@10206000 {
194300
compatible = "mediatek,mt7623-efuse",
195301
"mediatek,mt8173-efuse";
196-
reg = <0 0x10206000 0 0x1000>;
302+
reg = <0 0x10206000 0 0x1000>;
197303
#address-cells = <1>;
198304
#size-cells = <1>;
199305
thermal_calibration_data: calib@424 {
@@ -561,7 +667,8 @@
561667
};
562668

563669
u3phy1: usb-phy@1a1c4000 {
564-
compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy";
670+
compatible = "mediatek,mt7623-u3phy",
671+
"mediatek,mt2701-u3phy";
565672
reg = <0 0x1a1c4000 0 0x0700>;
566673
clocks = <&clk26m>;
567674
clock-names = "u3phya_ref";
@@ -599,7 +706,8 @@
599706
};
600707

601708
u3phy2: usb-phy@1a244000 {
602-
compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy";
709+
compatible = "mediatek,mt7623-u3phy",
710+
"mediatek,mt2701-u3phy";
603711
reg = <0 0x1a244000 0 0x0700>;
604712
clocks = <&clk26m>;
605713
clock-names = "u3phya_ref";
@@ -639,7 +747,9 @@
639747
};
640748

641749
eth: ethernet@1b100000 {
642-
compatible = "mediatek,mt2701-eth", "syscon";
750+
compatible = "mediatek,mt7623-eth",
751+
"mediatek,mt2701-eth",
752+
"syscon";
643753
reg = <0 0x1b100000 0 0x20000>;
644754
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
645755
<GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,

0 commit comments

Comments
 (0)