Skip to content

Commit b0f3cd3

Browse files
zming6666alexdeucher
zming6666
authored and
alexdeucher
committed
drm/amdgpu: remove unnecessary JPEG2.0 code from VCN2.0
They are no longer needed, using from JPEG2.0 instead. Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
1 parent 6ac2724 commit b0f3cd3

1 file changed

Lines changed: 3 additions & 257 deletions

File tree

‎drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c‎

Lines changed: 3 additions & 257 deletions
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,6 @@
7474

7575
static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
7676
static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
77-
static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);
7877
static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
7978
static int vcn_v2_0_set_powergating_state(void *handle,
8079
enum amd_powergating_state state);
@@ -97,7 +96,6 @@ static int vcn_v2_0_early_init(void *handle)
9796

9897
vcn_v2_0_set_dec_ring_funcs(adev);
9998
vcn_v2_0_set_enc_ring_funcs(adev);
100-
vcn_v2_0_set_jpeg_ring_funcs(adev);
10199
vcn_v2_0_set_irq_funcs(adev);
102100

103101
return 0;
@@ -132,12 +130,6 @@ static int vcn_v2_0_sw_init(void *handle)
132130
return r;
133131
}
134132

135-
/* VCN JPEG TRAP */
136-
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
137-
VCN_2_0__SRCID__JPEG_DECODE, &adev->vcn.inst->irq);
138-
if (r)
139-
return r;
140-
141133
r = amdgpu_vcn_sw_init(adev);
142134
if (r)
143135
return r;
@@ -194,19 +186,8 @@ static int vcn_v2_0_sw_init(void *handle)
194186
return r;
195187
}
196188

197-
ring = &adev->vcn.inst->ring_jpeg;
198-
ring->use_doorbell = true;
199-
ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
200-
sprintf(ring->name, "vcn_jpeg");
201-
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
202-
if (r)
203-
return r;
204-
205189
adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
206190

207-
adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
208-
adev->vcn.inst->external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH);
209-
210191
return 0;
211192
}
212193

@@ -258,11 +239,6 @@ static int vcn_v2_0_hw_init(void *handle)
258239
goto done;
259240
}
260241

261-
ring = &adev->vcn.inst->ring_jpeg;
262-
r = amdgpu_ring_test_helper(ring);
263-
if (r)
264-
goto done;
265-
266242
done:
267243
if (!r)
268244
DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
@@ -296,9 +272,6 @@ static int vcn_v2_0_hw_fini(void *handle)
296272
ring->sched.ready = false;
297273
}
298274

299-
ring = &adev->vcn.inst->ring_jpeg;
300-
ring->sched.ready = false;
301-
302275
return 0;
303276
}
304277

@@ -393,7 +366,6 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
393366
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
394367

395368
WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
396-
WREG32_SOC15(UVD, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
397369
}
398370

399371
static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect)
@@ -647,129 +619,6 @@ static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
647619
UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
648620
}
649621

650-
/**
651-
* jpeg_v2_0_start - start JPEG block
652-
*
653-
* @adev: amdgpu_device pointer
654-
*
655-
* Setup and start the JPEG block
656-
*/
657-
static int jpeg_v2_0_start(struct amdgpu_device *adev)
658-
{
659-
struct amdgpu_ring *ring = &adev->vcn.inst->ring_jpeg;
660-
uint32_t tmp;
661-
int r = 0;
662-
663-
/* disable power gating */
664-
tmp = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
665-
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_PGFSM_CONFIG), tmp);
666-
667-
SOC15_WAIT_ON_RREG(VCN, 0,
668-
mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
669-
UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
670-
671-
if (r) {
672-
DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
673-
return r;
674-
}
675-
676-
/* Removing the anti hang mechanism to indicate the UVDJ tile is ON */
677-
tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1;
678-
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), tmp);
679-
680-
/* JPEG disable CGC */
681-
tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
682-
tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
683-
tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
684-
tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
685-
WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp);
686-
687-
tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
688-
tmp &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
689-
| JPEG_CGC_GATE__JPEG2_DEC_MASK
690-
| JPEG_CGC_GATE__JPEG_ENC_MASK
691-
| JPEG_CGC_GATE__JMCIF_MASK
692-
| JPEG_CGC_GATE__JRBBM_MASK);
693-
WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, tmp);
694-
695-
/* enable JMI channel */
696-
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL), 0,
697-
~UVD_JMI_CNTL__SOFT_RESET_MASK);
698-
699-
/* enable System Interrupt for JRBC */
700-
WREG32_P(SOC15_REG_OFFSET(VCN, 0, mmJPEG_SYS_INT_EN),
701-
JPEG_SYS_INT_EN__DJRBC_MASK,
702-
~JPEG_SYS_INT_EN__DJRBC_MASK);
703-
704-
WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
705-
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
706-
WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
707-
lower_32_bits(ring->gpu_addr));
708-
WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
709-
upper_32_bits(ring->gpu_addr));
710-
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
711-
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
712-
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
713-
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
714-
ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
715-
716-
return 0;
717-
}
718-
719-
/**
720-
* jpeg_v2_0_stop - stop JPEG block
721-
*
722-
* @adev: amdgpu_device pointer
723-
*
724-
* stop the JPEG block
725-
*/
726-
static int jpeg_v2_0_stop(struct amdgpu_device *adev)
727-
{
728-
uint32_t tmp;
729-
int r = 0;
730-
731-
/* reset JMI */
732-
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL),
733-
UVD_JMI_CNTL__SOFT_RESET_MASK,
734-
~UVD_JMI_CNTL__SOFT_RESET_MASK);
735-
736-
/* enable JPEG CGC */
737-
tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
738-
tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
739-
tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
740-
tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
741-
WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp);
742-
743-
744-
tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
745-
tmp |= (JPEG_CGC_GATE__JPEG_DEC_MASK
746-
|JPEG_CGC_GATE__JPEG2_DEC_MASK
747-
|JPEG_CGC_GATE__JPEG_ENC_MASK
748-
|JPEG_CGC_GATE__JMCIF_MASK
749-
|JPEG_CGC_GATE__JRBBM_MASK);
750-
WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, tmp);
751-
752-
/* enable power gating */
753-
tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS));
754-
tmp &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;
755-
tmp |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF;
756-
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), tmp);
757-
758-
tmp = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
759-
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_PGFSM_CONFIG), tmp);
760-
761-
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS,
762-
(2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
763-
UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
764-
765-
if (r) {
766-
DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
767-
return r;
768-
}
769-
770-
return r;
771-
}
772-
773622
/**
774623
* vcn_v2_0_enable_clock_gating - enable VCN clock gating
775624
*
@@ -1052,12 +901,8 @@ static int vcn_v2_0_start(struct amdgpu_device *adev)
1052901
if (adev->pm.dpm_enabled)
1053902
amdgpu_dpm_enable_uvd(adev, true);
1054903

1055-
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1056-
r = vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);
1057-
if (r)
1058-
return r;
1059-
goto jpeg;
1060-
}
904+
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
905+
return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);
1061906

1062907
vcn_v2_0_disable_static_power_gating(adev);
1063908

@@ -1209,10 +1054,7 @@ static int vcn_v2_0_start(struct amdgpu_device *adev)
12091054
WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
12101055
WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
12111056

1212-
jpeg:
1213-
r = jpeg_v2_0_start(adev);
1214-
1215-
return r;
1057+
return 0;
12161058
}
12171059

12181060
static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)
@@ -1231,9 +1073,6 @@ static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)
12311073
tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
12321074
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code);
12331075

1234-
tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1235-
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1236-
12371076
tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
12381077
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
12391078

@@ -1252,10 +1091,6 @@ static int vcn_v2_0_stop(struct amdgpu_device *adev)
12521091
uint32_t tmp;
12531092
int r;
12541093

1255-
r = jpeg_v2_0_stop(adev);
1256-
if (r)
1257-
return r;
1258-
12591094
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
12601095
r = vcn_v2_0_stop_dpg_mode(adev);
12611096
if (r)
@@ -1781,56 +1616,6 @@ void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_
17811616
amdgpu_ring_write(ring, val);
17821617
}
17831618

1784-
/**
1785-
* vcn_v2_0_jpeg_ring_get_rptr - get read pointer
1786-
*
1787-
* @ring: amdgpu_ring pointer
1788-
*
1789-
* Returns the current hardware read pointer
1790-
*/
1791-
static uint64_t vcn_v2_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring)
1792-
{
1793-
struct amdgpu_device *adev = ring->adev;
1794-
1795-
return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR);
1796-
}
1797-
1798-
/**
1799-
* vcn_v2_0_jpeg_ring_get_wptr - get write pointer
1800-
*
1801-
* @ring: amdgpu_ring pointer
1802-
*
1803-
* Returns the current hardware write pointer
1804-
*/
1805-
static uint64_t vcn_v2_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
1806-
{
1807-
struct amdgpu_device *adev = ring->adev;
1808-
1809-
if (ring->use_doorbell)
1810-
return adev->wb.wb[ring->wptr_offs];
1811-
else
1812-
return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1813-
}
1814-
1815-
/**
1816-
* vcn_v2_0_jpeg_ring_set_wptr - set write pointer
1817-
*
1818-
* @ring: amdgpu_ring pointer
1819-
*
1820-
* Commits the write pointer to the hardware
1821-
*/
1822-
static void vcn_v2_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
1823-
{
1824-
struct amdgpu_device *adev = ring->adev;
1825-
1826-
if (ring->use_doorbell) {
1827-
adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1828-
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1829-
} else {
1830-
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
1831-
}
1832-
}
1833-
18341619
/**
18351620
* vcn_v2_0_jpeg_ring_insert_start - insert a start command
18361621
*
@@ -2071,9 +1856,6 @@ static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
20711856
case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
20721857
amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
20731858
break;
2074-
case VCN_2_0__SRCID__JPEG_DECODE:
2075-
amdgpu_fence_process(&adev->vcn.inst->ring_jpeg);
2076-
break;
20771859
default:
20781860
DRM_ERROR("Unhandled interrupt: %d %d\n",
20791861
entry->src_id, entry->src_data[0]);
@@ -2219,36 +2001,6 @@ static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {
22192001
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
22202002
};
22212003

2222-
static const struct amdgpu_ring_funcs vcn_v2_0_jpeg_ring_vm_funcs = {
2223-
.type = AMDGPU_RING_TYPE_VCN_JPEG,
2224-
.align_mask = 0xf,
2225-
.vmhub = AMDGPU_MMHUB_0,
2226-
.get_rptr = vcn_v2_0_jpeg_ring_get_rptr,
2227-
.get_wptr = vcn_v2_0_jpeg_ring_get_wptr,
2228-
.set_wptr = vcn_v2_0_jpeg_ring_set_wptr,
2229-
.emit_frame_size =
2230-
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2231-
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2232-
8 + /* vcn_v2_0_jpeg_ring_emit_vm_flush */
2233-
18 + 18 + /* vcn_v2_0_jpeg_ring_emit_fence x2 vm fence */
2234-
8 + 16,
2235-
.emit_ib_size = 22, /* vcn_v2_0_jpeg_ring_emit_ib */
2236-
.emit_ib = vcn_v2_0_jpeg_ring_emit_ib,
2237-
.emit_fence = vcn_v2_0_jpeg_ring_emit_fence,
2238-
.emit_vm_flush = vcn_v2_0_jpeg_ring_emit_vm_flush,
2239-
.test_ring = amdgpu_vcn_jpeg_ring_test_ring,
2240-
.test_ib = amdgpu_vcn_jpeg_ring_test_ib,
2241-
.insert_nop = vcn_v2_0_jpeg_ring_nop,
2242-
.insert_start = vcn_v2_0_jpeg_ring_insert_start,
2243-
.insert_end = vcn_v2_0_jpeg_ring_insert_end,
2244-
.pad_ib = amdgpu_ring_generic_pad_ib,
2245-
.begin_use = amdgpu_vcn_ring_begin_use,
2246-
.end_use = amdgpu_vcn_ring_end_use,
2247-
.emit_wreg = vcn_v2_0_jpeg_ring_emit_wreg,
2248-
.emit_reg_wait = vcn_v2_0_jpeg_ring_emit_reg_wait,
2249-
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2250-
};
2251-
22522004
static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
22532005
{
22542006
adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
@@ -2265,12 +2017,6 @@ static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev)
22652017
DRM_INFO("VCN encode is enabled in VM mode\n");
22662018
}
22672019

2268-
static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device *adev)
2269-
{
2270-
adev->vcn.inst->ring_jpeg.funcs = &vcn_v2_0_jpeg_ring_vm_funcs;
2271-
DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
2272-
}
2273-
22742020
static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = {
22752021
.set = vcn_v2_0_set_interrupt_state,
22762022
.process = vcn_v2_0_process_interrupt,

0 commit comments

Comments
 (0)