Make FlushICache NOP for Nvidia Denver 1.0 only

srikumarb · Commit bot · commit 434a291a0a05 · 2015-08-20T04:44:48.000Z
FlushICache should be NOP for Denver with part numbers 0x0, 0x1 and 0x2 only. Instruction cache needs to flushed for future versions of denver. Review URL: https://codereview.chromium.org/1287173004 Cr-Commit-Position: refs/heads/master@{#30262}
diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc
@@ -126,7 +126,8 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
   if (FLAG_enable_32dregs && cpu.has_vfp3_d32()) supported_ |= 1u << VFP32DREGS;
 
   if (cpu.implementer() == base::CPU::NVIDIA &&
-      cpu.variant() == base::CPU::NVIDIA_DENVER) {
+      cpu.variant() == base::CPU::NVIDIA_DENVER &&
+      cpu.part() <= base::CPU::NVIDIA_DENVER_V10) {
     supported_ |= 1u << COHERENT_CACHE;
   }
 #endif
diff --git a/src/arm64/assembler-arm64.cc b/src/arm64/assembler-arm64.cc
@@ -52,7 +52,8 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
   // Probe for runtime features
   base::CPU cpu;
   if (cpu.implementer() == base::CPU::NVIDIA &&
-      cpu.variant() == base::CPU::NVIDIA_DENVER) {
+      cpu.variant() == base::CPU::NVIDIA_DENVER &&
+      cpu.part() <= base::CPU::NVIDIA_DENVER_V10) {
     supported_ |= 1u << COHERENT_CACHE;
   }
 }
diff --git a/src/base/cpu.h b/src/base/cpu.h
@@ -59,6 +59,9 @@ class CPU final {
   static const int ARM_CORTEX_A12 = 0xc0c;
   static const int ARM_CORTEX_A15 = 0xc0f;
 
+  // Denver-specific part code
+  static const int NVIDIA_DENVER_V10 = 0x002;
+
   // PPC-specific part codes
   enum {
     PPC_POWER5,

Original file line number	Diff line number	Diff line change
`@@ -126,7 +126,8 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {`
`126`	`126`	`if (FLAG_enable_32dregs && cpu.has_vfp3_d32()) supported_ \|= 1u << VFP32DREGS;`
`127`	`127`
`128`	`128`	`if (cpu.implementer() == base::CPU::NVIDIA &&`
`129`		`- cpu.variant() == base::CPU::NVIDIA_DENVER) {`
	`129`	`+ cpu.variant() == base::CPU::NVIDIA_DENVER &&`
	`130`	`+ cpu.part() <= base::CPU::NVIDIA_DENVER_V10) {`
`130`	`131`	`supported_ \|= 1u << COHERENT_CACHE;`
`131`	`132`	`}`
`132`	`133`	`#endif`
Original file line number	Diff line number	Diff line change
`@@ -52,7 +52,8 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {`
`52`	`52`	`// Probe for runtime features`
`53`	`53`	`base::CPU cpu;`
`54`	`54`	`if (cpu.implementer() == base::CPU::NVIDIA &&`
`55`		`- cpu.variant() == base::CPU::NVIDIA_DENVER) {`
	`55`	`+ cpu.variant() == base::CPU::NVIDIA_DENVER &&`
	`56`	`+ cpu.part() <= base::CPU::NVIDIA_DENVER_V10) {`
`56`	`57`	`supported_ \|= 1u << COHERENT_CACHE;`
`57`	`58`	`}`
`58`	`59`	`}`