Welcome to the riscv-sodor wiki!

This repository has been put together to demonstrate a number of simple RISC-V integer pipelines written in the hardware construction language Chisel:

1-stage (essentially an ISA simulator)
2-stage (demonstrates pipelining in Chisel)
3-stage (uses sequential memory)
5-stage (can toggle between fully bypassed or fully interlocked)
"bus"-based micro-coded implementation

All of the cores implement the RISC-V 32b integer base user-level ISA (RV32I) version 2.0. Only the 1-stage and 3-stage implement a supervisor mode (RV32IS), enough to execute the RISC-V proxy kernel (riscv-pk).

All processors talk to a simple scratchpad memory (asynchronous, single-cycle), with no backing outer memory (the 3-stage is the exception - its scratchpad is synchronous). Programs are loaded in via a Host-target Interface (HTIF) port (while the core is kept in reset), effectively making the scratchpads 3-port memories (instruction, data, HTIF).

Here is the RISC-V 3-stage core, also known as the Z-Scale: