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cpackham-atlnzLinus Walleij
cpackham-atlnz
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Linus Walleij
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pinctrl: mvebu: pinctrl driver for 98DX2530 SoC
This pinctrl driver supports the 98DX25xx and 98DX35xx family of chips from Marvell. It is based on the Marvell SDK with additions for various (non-gpio) pin configurations based on the datasheet. Signed-off-by: Chris Packham <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
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‎drivers/pinctrl/mvebu/Kconfig‎

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@@ -45,6 +45,10 @@ config PINCTRL_ORION
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bool
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select PINCTRL_MVEBU
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config PINCTRL_AC5
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bool
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select PINCTRL_MVEBU
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config PINCTRL_ARMADA_37XX
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bool
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select GENERIC_PINCONF

‎drivers/pinctrl/mvebu/Makefile‎

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@@ -11,3 +11,4 @@ obj-$(CONFIG_PINCTRL_ARMADA_CP110) += pinctrl-armada-cp110.o
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obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o
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obj-$(CONFIG_PINCTRL_ARMADA_37XX) += pinctrl-armada-37xx.o
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obj-$(CONFIG_PINCTRL_ORION) += pinctrl-orion.o
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obj-$(CONFIG_PINCTRL_AC5) += pinctrl-ac5.o

‎drivers/pinctrl/mvebu/pinctrl-ac5.c‎

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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Marvell ac5 pinctrl driver based on mvebu pinctrl core
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*
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* Copyright (C) 2021 Marvell
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*
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* Noam Liron <[email protected]>
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-mvebu.h"
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static struct mvebu_mpp_mode ac5_mpp_modes[] = {
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MPP_MODE(0,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "sdio", "d0"),
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MPP_FUNCTION(2, "nand", "io4")),
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MPP_MODE(1,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "sdio", "d1"),
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MPP_FUNCTION(2, "nand", "io3")),
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MPP_MODE(2,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "sdio", "d2"),
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MPP_FUNCTION(2, "nand", "io2")),
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MPP_MODE(3,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "sdio", "d3"),
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MPP_FUNCTION(2, "nand", "io7")),
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MPP_MODE(4,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "sdio", "d4"),
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MPP_FUNCTION(2, "nand", "io6"),
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MPP_FUNCTION(3, "uart3", "txd"),
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MPP_FUNCTION(4, "uart2", "txd")),
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MPP_MODE(5,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "sdio", "d5"),
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MPP_FUNCTION(2, "nand", "io5"),
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MPP_FUNCTION(3, "uart3", "rxd"),
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MPP_FUNCTION(4, "uart2", "rxd")),
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MPP_MODE(6,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "sdio", "d6"),
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MPP_FUNCTION(2, "nand", "io0"),
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MPP_FUNCTION(3, "i2c1", "sck")),
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MPP_MODE(7,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "sdio", "d7"),
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MPP_FUNCTION(2, "nand", "io1"),
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MPP_FUNCTION(3, "i2c1", "sda")),
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MPP_MODE(8,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "sdio", "clk"),
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MPP_FUNCTION(2, "nand", "wen")),
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MPP_MODE(9,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "sdio", "cmd"),
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MPP_FUNCTION(2, "nand", "ale")),
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MPP_MODE(10,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "sdio", "ds"),
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MPP_FUNCTION(2, "nand", "cle")),
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MPP_MODE(11,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "sdio", "rst"),
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MPP_FUNCTION(2, "nand", "cen")),
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MPP_MODE(12,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "spi0", "clk")),
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MPP_MODE(13,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "spi0", "csn")),
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MPP_MODE(14,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "spi0", "mosi")),
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MPP_MODE(15,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "spi0", "miso")),
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MPP_MODE(16,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "spi0", "wpn"),
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MPP_FUNCTION(2, "nand", "ren"),
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MPP_FUNCTION(3, "uart1", "txd")),
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MPP_MODE(17,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "spi0", "hold"),
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MPP_FUNCTION(2, "nand", "rb"),
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MPP_FUNCTION(3, "uart1", "rxd")),
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MPP_MODE(18,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "tsen_int", NULL),
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MPP_FUNCTION(2, "uart2", "rxd"),
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MPP_FUNCTION(3, "wd_int", NULL)),
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MPP_MODE(19,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "dev_init_done", NULL),
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MPP_FUNCTION(2, "uart2", "txd")),
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MPP_MODE(20,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(2, "i2c1", "sck"),
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MPP_FUNCTION(3, "spi1", "clk"),
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MPP_FUNCTION(4, "uart3", "txd")),
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MPP_MODE(21,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(2, "i2c1", "sda"),
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MPP_FUNCTION(3, "spi1", "csn"),
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MPP_FUNCTION(4, "uart3", "rxd")),
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MPP_MODE(22,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(3, "spi1", "mosi")),
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MPP_MODE(23,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(3, "spi1", "miso")),
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MPP_MODE(24,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "wd_int", NULL),
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MPP_FUNCTION(2, "uart2", "txd"),
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MPP_FUNCTION(3, "uartsd", "txd")),
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MPP_MODE(25,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "int_out", NULL),
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MPP_FUNCTION(2, "uart2", "rxd"),
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MPP_FUNCTION(3, "uartsd", "rxd")),
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MPP_MODE(26,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "i2c0", "sck"),
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MPP_FUNCTION(2, "ptp", "clk1"),
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MPP_FUNCTION(3, "uart3", "txd")),
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MPP_MODE(27,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "i2c0", "sda"),
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MPP_FUNCTION(2, "ptp", "pulse"),
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MPP_FUNCTION(3, "uart3", "rxd")),
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MPP_MODE(28,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "xg", "mdio"),
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MPP_FUNCTION(2, "ge", "mdio"),
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MPP_FUNCTION(3, "uart3", "txd")),
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MPP_MODE(29,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "xg", "mdio"),
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MPP_FUNCTION(2, "ge", "mdio"),
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MPP_FUNCTION(3, "uart3", "rxd")),
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MPP_MODE(30,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "xg", "mdio"),
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MPP_FUNCTION(2, "ge", "mdio"),
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MPP_FUNCTION(3, "ge", "mdio")),
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MPP_MODE(31,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "xg", "mdio"),
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MPP_FUNCTION(2, "ge", "mdio"),
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MPP_FUNCTION(3, "ge", "mdio")),
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MPP_MODE(32,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "uart0", "txd")),
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MPP_MODE(33,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "uart0", "rxd"),
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MPP_FUNCTION(2, "ptp", "clk1"),
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MPP_FUNCTION(3, "ptp", "pulse")),
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MPP_MODE(34,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "ge", "mdio"),
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MPP_FUNCTION(2, "uart3", "rxd")),
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MPP_MODE(35,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "ge", "mdio"),
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MPP_FUNCTION(2, "uart3", "txd"),
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MPP_FUNCTION(3, "pcie", "rstoutn")),
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MPP_MODE(36,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "ptp", "clk0_tp"),
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MPP_FUNCTION(2, "ptp", "clk1_tp")),
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MPP_MODE(37,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "ptp", "pulse_tp"),
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MPP_FUNCTION(2, "wd_int", NULL)),
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MPP_MODE(38,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "synce", "clk_out0")),
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MPP_MODE(39,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "synce", "clk_out1")),
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MPP_MODE(40,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "ptp", "pclk_out0"),
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MPP_FUNCTION(2, "ptp", "pclk_out1")),
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MPP_MODE(41,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "ptp", "ref_clk"),
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MPP_FUNCTION(2, "ptp", "clk1"),
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MPP_FUNCTION(3, "ptp", "pulse"),
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MPP_FUNCTION(4, "uart2", "txd"),
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MPP_FUNCTION(5, "i2c1", "sck")),
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MPP_MODE(42,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "ptp", "clk0"),
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MPP_FUNCTION(2, "ptp", "clk1"),
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MPP_FUNCTION(3, "ptp", "pulse"),
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MPP_FUNCTION(4, "uart2", "rxd"),
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MPP_FUNCTION(5, "i2c1", "sda")),
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MPP_MODE(43,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "led", "clk")),
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MPP_MODE(44,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "led", "stb")),
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MPP_MODE(45,
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MPP_FUNCTION(0, "gpio", NULL),
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MPP_FUNCTION(1, "led", "data")),
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};
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static struct mvebu_pinctrl_soc_info ac5_pinctrl_info;
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static const struct of_device_id ac5_pinctrl_of_match[] = {
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{
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.compatible = "marvell,ac5-pinctrl",
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},
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{ },
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};
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static const struct mvebu_mpp_ctrl ac5_mpp_controls[] = {
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MPP_FUNC_CTRL(0, 45, NULL, mvebu_mmio_mpp_ctrl), };
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static struct pinctrl_gpio_range ac5_mpp_gpio_ranges[] = {
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MPP_GPIO_RANGE(0, 0, 0, 46), };
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static int ac5_pinctrl_probe(struct platform_device *pdev)
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{
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struct mvebu_pinctrl_soc_info *soc = &ac5_pinctrl_info;
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soc->variant = 0; /* no variants for ac5 */
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soc->controls = ac5_mpp_controls;
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soc->ncontrols = ARRAY_SIZE(ac5_mpp_controls);
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soc->gpioranges = ac5_mpp_gpio_ranges;
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soc->ngpioranges = ARRAY_SIZE(ac5_mpp_gpio_ranges);
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soc->modes = ac5_mpp_modes;
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soc->nmodes = ac5_mpp_controls[0].npins;
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pdev->dev.platform_data = soc;
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return mvebu_pinctrl_simple_mmio_probe(pdev);
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}
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static struct platform_driver ac5_pinctrl_driver = {
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.driver = {
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.name = "ac5-pinctrl",
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.of_match_table = of_match_ptr(ac5_pinctrl_of_match),
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},
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.probe = ac5_pinctrl_probe,
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};
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builtin_platform_driver(ac5_pinctrl_driver);

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