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Stars

rvv implementations

20 repositories

Ocelot: The Berkeley Out-of-Order Machine With V-EXT support

SystemVerilog 247 34 Updated Jan 14, 2026
Scala 314 43 Updated May 5, 2026

RISC-V Zve32x Vector Coprocessor

Assembly 216 59 Updated Jan 22, 2026

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

C 515 182 Updated May 5, 2026

This repo includes XiangShan's function units

Scala 30 14 Updated May 1, 2026

Open-source high-performance RISC-V processor

Scala 7,000 901 Updated May 6, 2026

Chisel RISC-V Vector 1.0 Implementation

Assembly 145 30 Updated Apr 23, 2026

SonicBOOM: The Berkeley Out-of-Order Machine

Scala 6 Updated Sep 26, 2024

Modified version of PULP Ara to support Vector Cryptography (Zvk) Instructions

SystemVerilog 18 3 Updated Jan 21, 2026
Scala 18 6 Updated Oct 6, 2025

Open-source high-performance RISC-V processor

Scala 32 19 Updated Dec 12, 2025
Emacs Lisp 7 3 Updated Mar 4, 2026
Scala 2 1 Updated Jan 25, 2024
Scala 11 6 Updated Jan 9, 2021

RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor

SystemVerilog 18 11 Updated Apr 8, 2026
SystemVerilog 8 Updated Jul 3, 2025
Verilog 1 1 Updated Sep 6, 2025

A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors

C 7 5 Updated Apr 29, 2026
SystemVerilog 2 1 Updated Feb 21, 2026

A machine learning accelerator core designed for energy-efficient AI at the edge.

Emacs Lisp 2,261 273 Updated May 5, 2026