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Microcode
sjsoftware edited this page Feb 3, 2023
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The microcode is a 56 bit mainly horizontal microcode controlled by AM2909 and AM2911 sequencers. Vertical aspects of the microcode are:
- Constants and conditional selection/update masks are stored in the same field as the direct inputs to the sequencers;
- The B Register Select field is used as inputs to two addressable latches;
- Control signals are encoded.
Bit 55 is MSB.
| Bit | Board Rom | PL Pins | Function | Comments |
|---|---|---|---|---|
| 3-0 | E3 | D2/D3 Decoder Input | Decoded before loaded into pipeline register. Data Bus select | |
| 6-4 | E3 | E6 Decoder Input | ||
| 7 | E3 | K11 Decoder Input bit 0 | ||
| 9-8 | J3 | K11 Decoder Input bit 1-2 | ||
| 12-10 | J3 | H11 Decoder Input | ||
| 14-13 | J3 | E7 Decoder Input | Pin 3 on decoder grounded | |
| 15 | J3 | J5 pin 2 | K9 multiplexer enable | Used for conditional calculation |
| 23-16 | M3 | Low 8 bits of sequencer direct input, constant input to data bus (inverted) | D2/D3 address 13 enables constant. Also used for conditional select and condition code update and low 3 bits for conditional JSR (microcode interrupt) | |
| 26-24 | L3 | High 3 bits of sequencer direct input | Also used for condition code update | |
| 27 | L3 | Sequencer stack enable (!FE) | ||
| 28 | L3 | Sequencer push or pop (PUP) | ||
| 30-29 | L3 | Sequencer 0-3 mux select (inverted) | ||
| 31 | L3 | Sequencer 4-7 mux select S0 (inverted) | ||
| 32 | H3 | H5 pin 19 | Sequencer 4-7 mux select S1/1 | |
| 33 | H3 | H5 pin 16 | Case control | |
| 36-34 | H3 | AM2901 I210 inputs | ||
| 39-37 | H3 | AM2901 I543 inputs | ||
| 42-40 | F3 | AM2901 I876 inputs | ||
| 46-43 | F3 | AM2901 B Register Select | Note also used as input to F11 and M13 'LS259 addressable latch for CPU control. Possibly also for M13 'LS259 | |
| 47 | F3 | AM2901 A Register Select bit 0 | A Register Select. | |
| 50-48 | K3 | AM2901 A Register Select bit 3-1 | ||
| 51 | K3 | Shift/Carry input to AM2901 mux S0 | ||
| 52 | K3 | Shift/Carry input to AM2901 mux S1 | ||
| 53 | K3 | K5 pin 15 | Hi/Low Register. | Controls whether high or low byte is read/written during register access |
| 54 | K3 | Sequencer 4-7 mux select S1/2 | Combines with bit 32 | |
| 55 | K3 | K5 pin 2 | Register at IPL | Determines whether Register index or IPL is used for register access |
Note: polarity on CPU Control signals may be incorrect
55 54 53 52-51 50-47 46-43 42-40 39-34 33 32-29 28-27 26-16 15 14-13 12-10 9-7 6-4 3-0
++ ++ ++ +---+ +---+ +---+ +---+ +---+ ++ +---+ +---+ +---+ ++ +---+ +---+ +-+ +-+ +-+
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | | +- Data Bus Select (1)
| | | | | | | | | | | | | | | | | 0: READ.SWP - read the swap register
| | | | | | | | | | | | | | | | | 1: READ.RF - read the register file pipeline register
| | | | | | | | | | | | | | | | | 2: READ.AHI - read the high byte of the logical address
| | | | | | | | | | | | | | | | | 3: READ.ALO - read the low byte of the logical address
| | | | | | | | | | | | | | | | | 8: READ.PF - read the current page file entry (current map)
| | | | | | | | | | | | | | | | | 9: READ.CCR - read the condition code register/sense switches (this might get renamed)
| | | | | | | | | | | | | | | | | 10: READ.DB - read the data bus from the AM2907 receive latches
| | | | | | | | | | | | | | | | | 11: READ.MSR - read the machine status register/current interrupt level (this might get renamed)
| | | | | | | | | | | | | | | | | 12: READ.INR - read the interrupt request level/dip switches (this might get renamed)
| | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | +----- Register Load (2)
| | | | | | | | | | | | | | | | 1: LOAD.RR - load result register, used to store ALU results
| | | | | | | | | | | | | | | | 2: LOAD.RIR - load register index register
| | | | | | | | | | | | | | | | 3: LOAD.ILR - load interrupt level register (this might get renamed)
| | | | | | | | | | | | | | | | 4: LOAD.MAP - load map register
| | | | | | | | | | | | | | | | 5: LOAD.MAR - load machine address register (PC)
| | | | | | | | | | | | | | | | 6: LOAD.SAR - load sequencer address register
| | | | | | | | | | | | | | | | 7: LOAD.CCR - load condition code register (this might get renamed)
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | +--------- Register Load (3)
| | | | | | | | | | | | | | | 1: DMA.RESET
| | | | | | | | | | | | | | | 2: CPU control 1 (B Register Select)
| | | | | | | | | | | | | | | 0/1: M13.0-/+ - unknown DMA control
| | | | | | | | | | | | | | | 2/3: M13.1-/+ - unknown DMA control
| | | | | | | | | | | | | | | 4/5: TIMER-/+ - timer enable/disable
| | | | | | | | | | | | | | | 6/7: PROM-/+ - instruction decode PROM disable (not used?)
| | | | | | | | | | | | | | | 8/9: RUN-/+ - run/halt light control
| | | | | | | | | | | | | | | 10/11: TIMER.RES-/+ - timer reset
| | | | | | | | | | | | | | | 12/13: ABORT-/+ - abort light control
| | | | | | | | | | | | | | | 14/15: IACK-/+ - interrupt acknowledge
| | | | | | | | | | | | | | | 3: CPU control 2 (B Register Select)
| | | | | | | | | | | | | | | 0/1: INT-/+ - interrupt enable/disable
| | | | | | | | | | | | | | | 2/3: ABE+/- - address bus enable/disable for high bits (not used?)
| | | | | | | | | | | | | | | 4/5: INC.DMA+/- - set DMA address and count to increment
| | | | | | | | | | | | | | | 6/7: DIR-/- - increment direction on address registers
| | | | | | | | | | | | | | | 8/9: DMA+/- - set DMA active (DMA ACK? might be renamed)
| | | | | | | | | | | | | | | 10/11: PARO-/+ - set even/odd parity
| | | | | | | | | | | | | | | 12/13: PE-/+ - enable/disable parity error
| | | | | | | | | | | | | | | 14/15: DMA.RD-/+ - DMA Ready (might be renamed)
| | | | | | | | | | | | | | | 4: WRITE.PF - write page file
| | | | | | | | | | | | | | | 5: WRITE.RF - write register file
| | | | | | | | | | | | | | | 6: LOAD.ALO - load address low byte
| | | | | | | | | | | | | | | 7: LOAD.DBR - load AM2907 transmit registers
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | +------------- Control (4)
| | | | | | | | | | | | | | 1: BUS.RD - Initiate a bus read cycle
| | | | | | | | | | | | | | 2: BUS.WT - Initiate a bus write cycle
| | | | | | | | | | | | | | 3: LOAD.AHI - load the high byte of the address register
| | | | | | | | | | | | | | 4: INC.WAR - increment the work address register
| | | | | | | | | | | | | | 5: INC.MAR - increment the machine address register (PC)
| | | | | | | | | | | | | | 6: PROME - enable the PROM for initial instruction decoding
| | | | | | | | | | | | | | 7: LOAD.SWP - load the swap register
| | | | | | | | | | | | | |
| | | | | | | | | | | | | +------------------- Control (5)
| | | | | | | | | | | | | 1: BUS.ABT - abort the current bus operation
| | | | | | | | | | | | | 2: LOAD.FLR - load ALU flags register
| | | | | | | | | | | | | 3: BUS.WAIT - wait for bus operation to complete
| | | | | | | | | | | | |
| | | | | | | | | | | | +------------------------- Conditional JSR (6)
| | | | | | | | | | | | 1: JSR - used with bits 2-0 of Constant field for conditional subroutine branch (microcode interrupt)
| | | | | | | | | | | | 0: JSR BUSY - DMA operation busy
| | | | | | | | | | | | 1: JSR EVEN - both nibbles of register index are even
| | | | | | | | | | | | 2: JSR ODD - low bit of register index is set
| | | | | | | | | | | | 3: JSR BADR - bad read address
| | | | | | | | | | | | 4: JSR BADW - bad write address
| | | | | | | | | | | | 5: JSR DMA - DMA request
| | | | | | | | | | | | 6: JSR PE - Parity error
| | | | | | | | | | | | 7: JSR INT - Interrupt
| | | | | | | | | | | +---------------------------- Constant/Sequencer Direct Inputs/Conditional branch control/Condition Code Update (7)
| | | | | | | | | | | Constants: Bits 23-16 inverted on to data path.
| | | | | | | | | | |
| | | | | | | | | | | Sequencer Direct Inputs: If Direct is specified for next sequencer address
| | | | | | | | | | | Conditional branch control: Bits 23-20 control condition, used with bit 33.
| | | | | | | | | | | Address bits 2/3
| | | | | | | | | | | 3: COND INT+/COND CCL - Interrupts enabled/Condition Code Link set
| | | | | | | | | | | 7: COND !DIN/COND !INT - DMA Interrupt/Interrupt (branch if not...) (these might get renamed)
| | | | | | | | | | | b: COND !DMA/DMAE - DMA Request (if not)/DMA Error (these might get renamed)
| | | | | | | | | | | Address bits 0/1
| | | | | | | | | | | c: COND SIGN/COND Z - Flags Minus (1100 xx10)/Zero (1100 xx01)
| | | | | | | | | | | d: COND HC/COND OVR - Flags Half Carry (1101 xx10)/Overflow (1101 xx01)
| | | | | | | | | | | e: COND GOOD/COND !BPG - Valid page (1110 xx10)/Write Ok (1110 xx01) (these might get renamed)
| | | | | | | | | | | Condition Code updates
| | | | | | | | | | | Bits 17-16 Zero/Sign (Value/Minus)
| | | | | | | | | | | 0: Keep
| | | | | | | | | | | 1: Flags zero/sign
| | | | | | | | | | | 2: Result Register bits 7/6
| | | | | | | | | | | 3: Flags 16 bit zero/sign
| | | | | | | | | | | Bits 20-18 Overflow (Fault)
| | | | | | | | | | | 0: Result Register bit 5
| | | | | | | | | | | 1: Set
| | | | | | | | | | | 2: Keep
| | | | | | | | | | | 3: Flags overflow
| | | | | | | | | | | 4-7: Clear
| | | | | | | | | | | Bits 24-21 Carry (Link)
| | | | | | | | | | | 0: Keep
| | | | | | | | | | | 2: Invert
| | | | | | | | | | | 4: Flags carry
| | | | | | | | | | | 6: Set
| | | | | | | | | | | 8: Result Register bit 4
| | | | | | | | | | | 10: ALU RAM7
| | | | | | | | | | | 12: ALU RAM0
| | | | | | | | | | | 14: ALU Q0
| | | | | | | | | | | Odd: Clear
| | | | | | | | | | |
| | | | | | | | | | +---------------------------------- Stack control (8)
| | | | | | | | | | 0: POP
| | | | | | | | | | 2: PUSH
| | | | | | | | | |
| | | | | | | | | +---------------------------------------- Sequencer control (with bit 54) (9)
| | | | | | | | | Complicated. For each of the three sequencers:
| | | | | | | | | S: Stack
| | | | | | | | | A: Address Register
| | | | | | | | | P: PC
| | | | | | | | | D: Direct Input
| | | | | | | | |
| | | | | | | | +---------------------------------------------- Conditional enable (10)
| | | | | | | | See bits 26-16
| | | | | | | |
| | | | | | | +------------------------------------------------- ALU Source and Operation (11)
| | | | | | | Arithmetic operations use carry in.
| | | | | | | 0: A+Q
| | | | | | | 1: A+B
| | | | | | | 2: Q+0
| | | | | | | 3: B+0
| | | | | | | 4: A+0
| | | | | | | 5: D+A
| | | | | | | 6: D+Q
| | | | | | | 7: D+0
| | | | | | | 8: Q-A-1
| | | | | | | 9: B-A-1
| | | | | | | 10: Q-1
| | | | | | | 11: B-1
| | | | | | | 12: A-1
| | | | | | | 13: A-D-1
| | | | | | | 14: Q-D-1
| | | | | | | 15: -D-1
| | | | | | | 16: A-Q-1
| | | | | | | 17: A-B-1
| | | | | | | 18: -Q-1
| | | | | | | 19: -B-1
| | | | | | | 20: -A-1
| | | | | | | 21: D-A-1
| | | | | | | 22: D-Q-1
| | | | | | | 23: D-1
| | | | | | | 24: A.OR.Q
| | | | | | | 25: A.OR.B
| | | | | | | 26: Q
| | | | | | | 27: B
| | | | | | | 28: A
| | | | | | | 29: D.OR.A
| | | | | | | 30: D.OR.Q
| | | | | | | 31: D
| | | | | | | 32: A.AND.Q
| | | | | | | 33: A.AND.B
| | | | | | | 34: ZERO
| | | | | | | 35: ZERO
| | | | | | | 36: ZERO
| | | | | | | 37: D.AND.A
| | | | | | | 38: D.AND.Q
| | | | | | | 39: ZERO
| | | | | | | 40: NOT.A.AND.Q
| | | | | | | 41: NOT.A.AND.B
| | | | | | | 42: Q
| | | | | | | 43: B
| | | | | | | 44: A
| | | | | | | 45: NOT.D.AND.A
| | | | | | | 46: NOT.D.AND.Q
| | | | | | | 47: ZERO
| | | | | | | 48: A.XOR.Q
| | | | | | | 49: A.XOR.B
| | | | | | | 50: Q
| | | | | | | 51: B
| | | | | | | 52: A
| | | | | | | 53: D.XOR.A
| | | | | | | 54: D.XOR.Q
| | | | | | | 55: D
| | | | | | | 56: A.EQV.Q
| | | | | | | 57: A.EQV.B
| | | | | | | 58: NOT.Q
| | | | | | | 59: NOT.B
| | | | | | | 60: NOT.A
| | | | | | | 61: D.EQV.A
| | | | | | | 62: D.EQV.Q
| | | | | | | 63: NOT.D
| | | | | | |
| | | | | | +------------------------------------------------------- ALU Destination (12)
| | | | | | 0: Q
| | | | | | 1: PASS (no storage)
| | | | | | 2: RAMA (store in B register, F=A)
| | | | | | 3: RAM (store in B register)
| | | | | | 4: RSHQ (store right shifted, right shift Q)
| | | | | | 5: RSH (store right shifted)
| | | | | | 6: LSHQ (store left shifted, left shift Q)
| | | | | | 7: LSH (store left shifted)
| | | | | |
| | | | | +------------------------------------------------------------- ALU B Register Select (13)
| | | | | r00 - r15. Also used for CPU control bit select
| | | | |
| | | | +------------------------------------------------------------------- ALU A Register Select (14)
| | | | r00 - r15
| | | |
| | | +------------------------------------------------------------------------- Shift/Carry input control (15)
| | | Carry
| | | 0: 0
| | | 1: 1
| | | 2: Flags carry
| | | 3: 0 (used with shift control)
| | |
| | | Left Shift (input to Q0)
| | | 0: 0
| | | 1: Flags carry
| | | 2: ALU carry out
| | | 3: 1
| | |
| | | Right Shift (input to RAM7)
| | | 0: RSAS ALU sign
| | | 1: RSFC Flags carry
| | | 2: RSQ0 Q0
| | | 3: RSQC ALU carry out
| | |
| | +------------------------------------------------------------------------------- Low byte for register file access (16)
| | 1: RLO - low byte of 16 bit register access
| |
| +---------------------------------------------------------------------------------- Sequencer control (with bits 32-29) (9)
| refer to sequencer control bits 32-29
|
+------------------------------------------------------------------------------------- Interrupt level for register file access (17)
1: I - use current interrupt level
The register file is a 256 x 8 SRAM block for 16 levels of 8 word or 16 byte registers. The register file has a pipeline register which is refreshed every cycle from the register file using the Register Index address combined with the low byte control and the interrupt level control.
E7 74LS138
| Address | Function | Notes |
|---|---|---|
| 0 | ||
| 1 | Bus operation abort | nor gate at E8 controlling E14 74LS74 pin 1 |
| 2 | Load FLR | enable on J9 74LS378 |
| 3 | Bus wait | nor gate at E8 |
| 4 | unused | pin 3 on E7 is grounded |
| 5 | unused | pin 3 on E7 is grounded |
| 6 | unused | pin 3 on E7 is grounded |
| 7 | unused | pin 3 on E7 is grounded |
H11 74LS138
| Address | Function | Notes |
|---|---|---|
| 0 | ||
| 1 | Bus Read | |
| 2 | Bus Write | |
| 3 | Load Work AR High | Enables load on the high word of the work AR 'LS669s |
| 4 | Increment/decrement Work AR | |
| 5 | Increment/decrement MAR | |
| 6 | PROM enable/ALU disable | |
| 7 | Load Nibble Swapper | C11 and C12 |
K11 74LS138
| Address | Function | Notes |
|---|---|---|
| 0 | ||
| 1 | ||
| 2 | M13 'LS259 enable | enables latching to start/stop CPU operations |
| 3 | F11 'LS259 enable | enables latching to start/stop CPU operations |
| 4 | Register write | Same decoding in basic gates with alternate clocking |
| 5 | Load Page File | Loads the Result Register into the page file |
| 6 | Load Work AR Low | Enables load on the low word of the work AR 'LS669s (consistent with microcode) |
| 7 | Load Data Register | Tx register on AM2907s |
E6 74LS138
| Address | Function | Notes |
|---|---|---|
| 0 | ||
| 1 | Load RR | Load data register used for updating lots of things ('LS377 at C9) |
| 2 | Load RIR | Load register index ('LS377 at C13) |
| 3 | Load CLR | Interrupt Level |
| 4 | Load MAP | Load PT MAP register. Used with address lines for PT entry address |
| 5 | Load MAR | Load Memory Address Register (outer 'LS669s) from work address register (inner 'LS669s) |
| 6 | Load Seq AR | Load the sequencer AR. Likely only on the AM2909s |
| 7 | Load CCR | Load CC based on CONST field in microcode |
D2 74S139 (half) and D3 74S138
Note that these addresses get decoded before storage in the pipeline register.
| Address | Function | Notes |
|---|---|---|
| 0 | Read Swapped | Enable on C11/12 'LS173 tristate ffs |
| 1 | Read Register | Read the contents of the ISA register from D14 'LS374 |
| 2 | Read Address High | Read high byte of bus address before page lookup (real PC). Note bits 12-15 inverted |
| 3 | Read Address Low | Read low byte of bus address |
| 4 | Unused | |
| 5 | Unused | |
| 6 | Unused | |
| 7 | Unused | |
| 8 | Read Page | Read the page address (top 7 bits of paged address + MMIO select) |
| 9 | Read CCR | Read sense switches (1-4) low nibble and condition codes high nibble |
| 10 | Read Data Bus | AM2907s |
| 11 | Read Current Level | Enable on 'LS368 tristate inverter H14 and T18-21 from backplane bus |
| 12 | Read Req Level | Read other dip switches switches low nibble and interrupt request level from backplane high nibble |
| 13 | Constant | Constant from microcode word (inverted) |
| 14 | Unused | |
| 15 | Unused |
F11 lines
| Address | B select | Function |
|---|---|---|
| 0 | 0, 1 | Interrupt enable (on = enabled). Controlled by EI/DI instructions |
| 1 | 2, 3 | Address Bus enable (off = enabled) |
| 2 | 4, 5 | DMA address increment control? |
| 3 | 6, 7 | Increment/Decrement control of address register Off is decrement |
| 4 | 8, 9 | DMA control? |
| 5 | 10, 11 | Controlled by 96/a6 instructions. Parity Odd/Even? |
| 6 | 12, 13 | Controlled by 76/86 instructions. Parity check enabled (on = enabled) |
| 7 | 14, 15 | DMA enable (on). Controlled by 2f x6/x7 instruction. x6 enables |
M13 lines
| Address | B select | Function |
|---|---|---|
| 0 | 0, 1 | DMA function, controlled by 2f x4/x5 instruction |
| 1 | 2, 3 | DMA function, controlled by 2f x4/x5 instruction |
| 2 | 4, 5 | Timer (RTC) enable |
| 3 | 6, 7 | |
| 4 | 8, 9 | Run/Halt front panel light |
| 5 | 10, 11 | Timer reset (off = reset) |
| 6 | 12, 13 | ABT front panel light |
| 7 | 14, 15 | Interrupt acknowledge |
| Shift/Carry | Carry | Left Shift | Right Shift |
|---|---|---|---|
| 0 | 0 | 0 | ALU sign (F3 on high nibble) |
| 1 | 1 | Flags Carry | Flags Carry |
| 2 | Flags Carry | ALU Sign | ALU Q0 |
| 3 | 0 | 1 | ALU Carry |
Conditional branches, subroutine calls and condition code register setting is controlled by the microcode address/constant field.
The condition code register Link/Carry bit is set from bits 24 to 21 in the microcode word. Bit 21 disables the multiplexer and will force the link bit to be set to zero in the condition code register. This is implemented by an 8 to 1 multiplexer at J10 on the CPU6 board.
The fault/overflow bit in the condition code register is set based on bits 20 and 19 in the microcode word, and the fault field from the last ALU flags storage. Bit 18 disables the multiplexer and will force the fault bit to be set to zero in the condition code register. This is implemented by an 8 to 1 multiplexer at J11 on the CPU6 board.
These flags are set from the same multiplexer, which is always enabled. The values are set based on bits 17 and 16 in the microcode word. This is implemented by a dual 4 to 1 multiplexer at J12 on the CPU6 board.
The conditional branches in the microcode are controlled by two multiplexers which set the OR lines in the low nibble AM2909. The multiplexer selects are the from bits 18 - 16 of the microcode word, and the enable is bit 33 of the microcode word. Usually only one OR line is significant on any conditional branch, other lines if active are masked out with the microcode address low nibble (e.g., if it is a conditional branch zero, there will be a mask of xx01 in the low nibble of the microcode address field). OR 0 and OR 1 are set by a dual 4 to 1 multiplexer at J13 on the CPU6 board. OR 2 and 3 are set by a dual 4 to 1 multiplexer at K13 on the CPU6 board.
Most of the conditional branches are one way (only one bit of the multiplexer output is relevant), but there are five microcode locations where there is a multiway branch.
Microcode conditional subroutine calls are controlled by a multiplexer which is selected from bits 2 to 0 of the microcode address field. This is also used to form part of the subroutine address. The conditional subroutine call is enabled by bit 15 of the microcode word. The conditions are selected by a multiplexer at K9 on the CPU6 board.