The bias_pll_cc_clk and bias_pll_nss_noc_clk fixed clocks are mentioned
as parents of some IPQ6018 GCC clock tree nodes. Add their definition
based on downstream kernel.

Signed-off-by: Baruch Siach <[email protected]>

Add 'name' to parent data to allow clk_set_parent find parent clocks by
name. Otherwise, clk_core_lookup() can't find parent clocks.

Signed-off-by: Baruch Siach <[email protected]>

Signed-off-by: anusha <[email protected]>
Change-Id: I85bb1c127a4794ae9347d5babbbfd6490f6abcc7

Included CLK_IS_CRITICAL flag which helps to properly enable
the APSS PLL during bootup.

clk_rcg2_ops should be used for APSS clock RCG, other ops
will not configure the RCG register.

Signed-off-by: Praveenkumar I <[email protected]>
Change-Id: I5fa8b6440a310564adb9da82d4992c00241405ce

Without the critical flag, below warning is seen when QDSS
components are enabled.

[    1.712722] ------------[ cut here ]------------
[    1.719039] gcc_qdss_dap_clk status stuck at 'on'
[    1.719084] WARNING: CPU: 1 PID: 1 at drivers/clk/qcom/clk-branch.c:92 clk_branch_toggle+0x160/0x178

Signed-off-by: Kathiravan T <[email protected]>
Change-Id: Id3a7fe5e240464eb6e5aff6c6c7343f103b009f4

the round rate clock API has a limitation that it cannot operate above the
frequency of signed long. The clock controller treats the frequency
above signed long max as an error.

use determine rate API which treats frequency and error code separately.

Signed-off-by: Sivaprakash Murugesan <[email protected]>
Change-Id: I0b3f6c33adac35a4b249efb1e586da3426f959da

qcomsmempart uses the mtd_info erasesize field to calculate partitions
offset and size based on SMEM provided number. When
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is enabled erasesize does not show the
actual hardware block size.

Unfortunately, N366 SPI flash partition table depends on 4K sectors,
because we have partitions with 4K size. Without 4K sectors these
partition become read-only at boot.

Set the block size to 64K, which is usually the case for SPI flashes.

Driver for the PWM block in Qualcomm IPQ6018 line of SoCs. Based on
driver from downstream Codeaurora kernel tree. Removed support for older
(V1) variants because I have no access to that hardware.

Tested on IPQ6010 based hardware.

Signed-off-by: Baruch Siach <[email protected]>
---
v10:

  Restore round up in pwm_div calculation; otherwise diff is always <=
  0, so only bingo match works

  Don't overwrite min_diff on every loop iteration

v9:

Address comment from Uwe Kleine-König:

  Use period_ns*rate in dividers calculation for better accuracy

  Round down pre_div and pwm_div

  Add a comment explaining why pwm_div can't underflow

  Add a comment explaining why pre_div > pwm_div end the search loop

  Drop 'CFG_' from register macros

  Rename to_ipq_pwm_chip() to ipq_pwm_from_chip()

  Change bare 'unsigned' to 'unsigned int'

  Clarify the comment on separate REG1 write for enable/disable

  Round up the period value in .get_state

  Use direct readl/writel so no need to check for regmap errors

v7:

  Change 'offset' to 'reg' for the tcsr offset (Rob)

  Drop clock name; there is only one clock (Bjorn)

  Simplify probe failure code path (Bjorn)

v6:

Address Uwe Kleine-König review comments:

  Drop IPQ_PWM_MAX_DEVICES

  Rely on assigned-clock-rates; drop IPQ_PWM_CLK_SRC_FREQ

  Simplify register offset calculation

  Calculate duty cycle more precisely

  Refuse to set inverted polarity

  Drop redundant IPQ_PWM_REG1_ENABLE bit clear

  Remove x1000 factor in pwm_div calculation, use rate directly, and round up

  Choose initial pre_div such that pwm_div < IPQ_PWM_MAX_DIV

  Ensure pre_div <= pwm_div

  Rename close_ to best_

  Explain in comment why effective_div doesn't overflow

  Limit pwm_div to IPQ_PWM_MAX_DIV - 1 to allow 100% duty cycle

  Disable clock only after pwmchip_remove()

  const pwm_ops

Other changes:

  Add missing linux/bitfield.h header include (kernel test robot)

  Adjust code for PWM device node under TCSR (Rob Herring)

v5:

Use &tcsr_q6 syscon to access registers (Bjorn Andersson)

Address Uwe Kleine-König review comments:

  Implement .get_state()

  Add IPQ_PWM_ prefix to local macros

  Use GENMASK/BIT/FIELD_PREP for register fields access

  Make type of config_div_and_duty() parameters consistent

  Derive IPQ_PWM_MIN_PERIOD_NS from IPQ_PWM_CLK_SRC_FREQ

  Integrate enable/disable into config_div_and_duty() to save register read,
  and reduce frequency glitch on update

  Use min() instead of min_t()

  Fix comment format

  Use dev_err_probe() to indicate probe step failure

  Add missing clk_disable_unprepare() in .remove

  Don't set .owner

v4:

  Use div64_u64() to fix link for 32-bit targets ((kernel test robot
  <[email protected]>, Uwe Kleine-König)

v3:

  s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring)

  Fix integer overflow on 32-bit targets (kernel test robot <[email protected]>)

v2:

Address Uwe Kleine-König review comments:

  Fix period calculation when out of range

  Don't set period larger than requested

  Remove PWM disable on configuration change

  Implement .apply instead of non-atomic .config/.enable/.disable

  Don't modify PWM on .request/.free

  Check pwm_div underflow

  Fix various code and comment formatting issues

Other changes:

  Use u64 divisor safe division

  Remove now empty .request/.free

Describe the PWM block on IPQ6018.

The PWM is in the TCSR area. Make &tcsr "simple-mfd" compatible, and add
&pwm as child of &tcsr.

Add also ipq6018 specific compatible string.

This reverts commit 8f62f59 because it
invalidates commit a51fe27
(mtd: qcomsmempart: workaround SPI flash 4K_SECTORS)