ESP32-C5 hardware qualification and cadence follow-up

Firmware is published as an experimental prerelease: https://github.com/ruvnet/RuView/releases/tag/v0.8.17-esp32

Merged firmware/install PR: #2382. Merged SDK monitor and measured guides: #2389.

Completed

• Production ESP32-C5HR8 revision 1.2, 8 MB flash and 8 MB embedded PSRAM identified.
• Full original 8 MB flash preserved privately at 115200 baud; separate 64 KiB sample readback matched.
• Fixed legacy mmWave GPIO17/18 probing that collided with C5 flash/PSRAM and caused watchdog/flash-busy loops.
• Added pin-guard and installer/SDK monitor regression tests; failures cannot be hidden by initial CSI callbacks.
• Installed firmware 0.8.17, provisioned WiFi privately, and restored normal UDP target port 5005.
• Exercised production SDK serial and UDP paths on the attached device.
• Merged both PRs after required checks passed.
• Published all four firmware variant archives and SHA256SUMS.txt from exact-run CI artifacts.
• Verified archive safety, outer/inner hashes, embedded versions/chip IDs and C5 exact-run byte identity.
• Installed the final release C5 bundle on COM8; serial monitor passed and all 479 packets decoded in a final 30-second sample (371 raw CSI, no unknown/malformed packets).
• Verified anonymous C5 archive download returned HTTP 200 and the expected hash.

Successful firmware release workflow: https://github.com/ruvnet/RuView/actions/runs/40915261010
Commit/tag target: 5728b90

MEASURED (bounded real hardware): A separate five-minute corrected-firmware sample decoded all 5,318 packets, including 4,197 raw CSI frames, with no unknown/malformed packets or captured firmware faults/disconnects. Raw cadence averaged 13.99 packets/s in that run. Earlier bounded samples reached about 29 packets/s; extra 50/100 Hz small-packet and 50 Hz larger-packet stimuli did not produce consistent improvement. No traffic generator remains running.

Open qualification limits

• Establish a repeatable >=20 raw packets/s profile on this AP and explain cadence variability.
• Confirm the exact board form factor and test other boards under matched conditions.
• Longer stability and reference-based sensing-accuracy validation.

C5 remains experimental. Retained profile: 2.4 GHz, 240 MHz CPU, 8 Hz edge DSP, 4 MB OTA layout, LED/display/WASM/PSRAM disabled. 5 GHz, sensing accuracy and a general C5-versus-C6 speedup are not qualified. Historical C6 measurements used different firmware/AP conditions.

The npm harness 0.9.3 publication is independently blocked by registry authorization: #2390. Use the checked-out main source installer for C5 support meanwhile.

Keep credentials, identifiers, backups and raw RF/vital data private.

• Guide: https://github.com/ruvnet/RuView/blob/main/docs/user-guide.md#esp32-c5-experimental-csi-target
• Full record: https://github.com/ruvnet/RuView/blob/main/docs/validation/2026-10-28-esp32-c5-candidate.md
• Gist: https://gist.github.com/ruvnet/bacfc5ac6b4feed7cfc1f76c03d12f4c

MEASURED compatibility with the previous server image

The real C5 on released firmware also passed a live test against ghcr.io/ruvnet/wifi-densepose:v0.8.16-esp32 (revision 3686bc7): health HTTP 200, unauthenticated API HTTP 401, authenticated API HTTP 200, C5 node active and its CSI sequence advancing. The temporary container was stopped after the test. This is software/transport compatibility evidence, not a matched ESP32 hardware-performance comparison or sensing-accuracy qualification. Local API requests used a direct loopback connection; the host HTTP proxy had caused the first health probe to time out.